Lines Matching +full:0 +full:x010

31 #define CMD_QUEUE_MASK_OFFSET		0x000
32 #define CMD_QUEUE_PRIO_OFFSET		0x004
33 #define CMD_REQID_CONFIG_OFFSET		0x008
34 #define TRNG_OUT_OFFSET			0x00C
35 #define CMD_CMD_TIMEOUT_OFFSET		0x010
36 #define LSB_PUBLIC_MASK_LO_OFFSET	0x018
37 #define LSB_PUBLIC_MASK_HI_OFFSET	0x01C
38 #define LSB_PRIVATE_MASK_LO_OFFSET	0x020
39 #define LSB_PRIVATE_MASK_HI_OFFSET	0x024
41 #define VERSION_REG			0x100
42 #define VERSION_NUM_MASK		0x3F
43 #define VERSION_CAP_MASK		0x7FC0
54 #define VERSION_NUMVQM_MASK		0xF
56 #define VERSION_LSBSIZE_MASK		0x3FF
58 #define CMD_Q_CONTROL_BASE		0x000
59 #define CMD_Q_TAIL_LO_BASE		0x004
60 #define CMD_Q_HEAD_LO_BASE		0x008
61 #define CMD_Q_INT_ENABLE_BASE		0x00C
62 #define CMD_Q_INTERRUPT_STATUS_BASE	0x010
64 #define CMD_Q_STATUS_BASE		0x100
65 #define CMD_Q_INT_STATUS_BASE		0x104
67 #define CMD_Q_STATUS_INCR		0x1000
70 #define CMD_CONFIG_0_OFFSET		0x6000
71 #define CMD_TRNG_CTL_OFFSET		0x6008
72 #define CMD_AES_MASK_OFFSET		0x6010
73 #define CMD_CLK_GATE_CTL_OFFSET		0x603C
76 #define CMD_Q_RUN			(1 << 0)
80 #define CMD_Q_SIZE_MASK			0x1F
82 #define CMD_Q_PTR_HI_MASK		0xFFFF
88 #define INT_COMPLETION			(1 << 0)
97 #define STATUS_ERROR_MASK		0x3F
99 #define STATUS_JOBSTATUS_MASK		0x7
101 #define STATUS_ERRORSOURCE_MASK		0x3
103 #define STATUS_VLSB_FAULTBLOCK_MASK	0x7
106 #define JOBSTATUS_IDLE			0
114 #define ERRORSOURCE_INPUT_MEMORY	0
122 	CCP_AES_MODE_ECB = 0,
138 	CCP_AES_MODE_GHASH_AAD = 0,
143 	CCP_AES_TYPE_128 = 0,
149 	CCP_DES_MODE_ECB = 0,
155 	CCP_DES_TYPE_128 = 0,	/* 112 + 16 parity */
174 	CCP_CIPHER_ALGO_AES_CBC = 0,
182 	CCP_CIPHER_DIR_DECRYPT = 0,
187 	CCP_AUTH_ALGO_SHA1 = 0,
210 	CCP_AUTH_OP_GENERATE = 0,
215 	CCP_ENGINE_AES = 0,
226 	CCP_XTS_AES_UNIT_SIZE_16 = 0,
234 	CCP_PASSTHRU_BITWISE_NOOP = 0,
242 	CCP_PASSTHRU_BYTESWAP_NOOP = 0,
250  * word 0: function; engine; control bits
418 	CCP_MEMTYPE_SYSTEM = 0,
424 	CCP_CMD_CIPHER = 0,