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/linux/sound/soc/tegra/
H A Dtegra210_sfc.c27 { TEGRA210_SFC_RX_INT_MASK, 0x00000001},
28 { TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},
29 { TEGRA210_SFC_TX_INT_MASK, 0x00000001},
30 { TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},
31 { TEGRA210_SFC_CG, 0x1},
32 { TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},
53 0x000c6102,//header
54 0x0001d727,//input gain
55 0x00fc2fc7, 0xff9bb27b, 0x001c564c,
56 0x00e55557, 0xffcadd5b, 0x003d80ba,
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-lp-sk-nand.dtso19 AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
20 AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
21 AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
22 AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
23 AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
24 AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
25 AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
26 AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
27 AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
28 AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
[all …]
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-am642-evm-nand.dtso18 AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
19 AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */
20 AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */
21 AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */
22 AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */
23 AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */
24 AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */
25 AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */
26 AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */
27 AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */
[all …]
/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_save_dump.h_shipped7 0x20805000,
8 0x20805201,
9 0x20805402,
10 0x20805603,
11 0x20805804,
12 0x20805a05,
13 0x20805c06,
14 0x20805e07,
15 0x20806008,
16 0x20806209,
[all …]
/linux/arch/powerpc/boot/dts/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
/linux/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dibm,ndfc.txt5 - reg : should specify chip select and size used for the chip (0x2000).
8 - ccr : NDFC config and control register value (default 0).
9 - bank-settings : NDFC bank configuration register value (default 0).
16 ndfc@1,0 {
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
28 partition@0 {
30 reg = <0x00000000 0x00200000>;
34 reg = <0x00200000 0x03E00000>;
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/arch/arm/mach-mmp/
H A Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dcputable.h6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
[all …]
/linux/arch/arm/mach-rpc/include/mach/
H A Dhardware.h25 #define RPC_RAM_SIZE 0x10000000
26 #define RPC_RAM_START 0x10000000
28 #define EASI_SIZE 0x08000000 /* EASI I/O */
29 #define EASI_START 0x08000000
30 #define EASI_BASE IOMEM(0xe5000000)
32 #define IO_START 0x03000000 /* I/O */
33 #define IO_SIZE 0x01000000
34 #define IO_BASE IOMEM(0xe0000000)
36 #define SCREEN_START 0x02000000 /* VRAM */
37 #define SCREEN_END 0xdfc00000
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/vfn/
H A Dga100.c30 { NVKM_ENGINE_DISP , 0, 4, 0x04000000, true },
31 { NVKM_SUBDEV_GPIO , 0, 4, 0x00200000, true },
32 { NVKM_SUBDEV_I2C , 0, 4, 0x00200000, true },
33 { NVKM_SUBDEV_PRIVRING, 0, 4, 0x40000000, true },
41 .user = { 0x030000, 0x010000, { -1, -1, AMPERE_USERMODE_A } },
49 return r535_vfn_new(&ga100_vfn, device, type, inst, 0xb80000, pvfn); in ga100_vfn_new()
51 return nvkm_vfn_new_(&ga100_vfn, device, type, inst, 0xb80000, pvfn); in ga100_vfn_new()
/linux/drivers/crypto/
H A Dtalitos.h12 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
13 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
14 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
159 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
160 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
161 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
162 #define TALITOS_FTR_HMAC_OK 0x00000008
163 #define TALITOS_FTR_SEC1 0x00000010
187 #define TALITOS_MCR 0x1030 /* master control register */
188 #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
[all …]
/linux/drivers/net/ethernet/sis/
H A Dsis900.h19 #define SIS900_TOTAL_SIZE 0x100
23 cr=0x0, //Command Register
24 cfg=0x4, //Configuration Register
25 mear=0x8, //EEPROM Access Register
26 ptscr=0xc, //PCI Test Control Register
27 isr=0x10, //Interrupt Status Register
28 imr=0x14, //Interrupt Mask Register
29 ier=0x18, //Interrupt Enable Register
30 epar=0x18, //Enhanced PHY Access Register
31 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dnv50.c28 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
29 { NVKM_ENGINE_GR , 0, 0, 0x00001000, true },
30 { NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
31 { NVKM_ENGINE_MPEG , 0, 0, 0x00000001, true },
32 { NVKM_SUBDEV_FB , 0, 0, 0x00001101, true },
33 { NVKM_SUBDEV_BUS , 0, 0, 0x10000000, true },
34 { NVKM_SUBDEV_GPIO , 0, 0, 0x00200000, true },
35 { NVKM_SUBDEV_I2C , 0, 0, 0x00200000, true },
36 { NVKM_SUBDEV_TIMER, 0, 0, 0x00100000, true },
44 nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */ in nv50_mc_init()
H A Dgk104.c28 { 0x00000100, NVKM_ENGINE_FIFO },
29 { 0x00002000, NVKM_SUBDEV_PMU, 0, true },
35 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
36 { NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
37 { NVKM_SUBDEV_PRIVRING, 0, 0, 0x40000000, true },
38 { NVKM_SUBDEV_BUS , 0, 0, 0x10000000, true },
39 { NVKM_SUBDEV_FB , 0, 0, 0x08002000, true },
40 { NVKM_SUBDEV_LTC , 0, 0, 0x02000000, true },
41 { NVKM_SUBDEV_PMU , 0, 0, 0x01000000, true },
42 { NVKM_SUBDEV_GPIO , 0, 0, 0x00200000, true },
[all …]
H A Dg98.c28 { 0x04008000, NVKM_ENGINE_MSVLD },
29 { 0x02004000, NVKM_ENGINE_SEC },
30 { 0x01020000, NVKM_ENGINE_MSPDEC },
31 { 0x00400002, NVKM_ENGINE_MSPPP },
32 { 0x00201000, NVKM_ENGINE_GR },
33 { 0x00000100, NVKM_ENGINE_FIFO },
39 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
40 { NVKM_ENGINE_MSPDEC, 0, 0, 0x00020000, true },
41 { NVKM_ENGINE_MSVLD , 0, 0, 0x00008000, true },
42 { NVKM_ENGINE_SEC , 0, 0, 0x00004000, true },
[all …]
H A Dg84.c28 { 0x04008000, NVKM_ENGINE_BSP },
29 { 0x02004000, NVKM_ENGINE_CIPHER },
30 { 0x01020000, NVKM_ENGINE_VP },
31 { 0x00400002, NVKM_ENGINE_MPEG },
32 { 0x00201000, NVKM_ENGINE_GR },
33 { 0x00000100, NVKM_ENGINE_FIFO },
39 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
40 { NVKM_ENGINE_VP , 0, 0, 0x00020000, true },
41 { NVKM_ENGINE_BSP , 0, 0, 0x00008000, true },
42 { NVKM_ENGINE_CIPHER, 0, 0, 0x00004000, true },
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-ts219.dtsi8 reg = <0x00000000 0x20000000>;
23 reg = <0x30>;
34 reg = <0x12100 0x100>;
40 m25p128@0 {
44 reg = <0>;
46 mode = <0>;
48 partition@0 {
49 reg = <0x00000000 0x00080000>;
54 reg = <0x00200000 0x00200000>;
59 reg = <0x00400000 0x00900000>;
[all …]

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