Lines Matching +full:0 +full:x00200000
54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
65 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
66 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
67 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
68 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
69 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
70 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
71 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
72 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
73 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
74 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>,
75 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
81 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
82 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
83 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
84 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
85 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
86 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
87 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
88 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
89 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
90 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
91 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
92 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
99 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;