1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ae150435SJeff Kirsher /*************************************************************************** 3ae150435SJeff Kirsher * 4ae150435SJeff Kirsher * Copyright (C) 2004-2008 SMSC 5ae150435SJeff Kirsher * Copyright (C) 2005-2008 ARM 6ae150435SJeff Kirsher * 7ae150435SJeff Kirsher ***************************************************************************/ 8ae150435SJeff Kirsher #ifndef __SMSC911X_H__ 9ae150435SJeff Kirsher #define __SMSC911X_H__ 10ae150435SJeff Kirsher 11f6fec61eSDavid Cai /*Chip ID*/ 12f6fec61eSDavid Cai #define LAN9115 0x01150000 13f6fec61eSDavid Cai #define LAN9116 0x01160000 14f6fec61eSDavid Cai #define LAN9117 0x01170000 15f6fec61eSDavid Cai #define LAN9118 0x01180000 16f6fec61eSDavid Cai #define LAN9215 0x115A0000 17f6fec61eSDavid Cai #define LAN9216 0x116A0000 18f6fec61eSDavid Cai #define LAN9217 0x117A0000 19f6fec61eSDavid Cai #define LAN9218 0x118A0000 20f6fec61eSDavid Cai #define LAN9210 0x92100000 21f6fec61eSDavid Cai #define LAN9211 0x92110000 22f6fec61eSDavid Cai #define LAN9220 0x92200000 23f6fec61eSDavid Cai #define LAN9221 0x92210000 24f6fec61eSDavid Cai #define LAN9250 0x92500000 25f6fec61eSDavid Cai #define LAN89218 0x218A0000 26f6fec61eSDavid Cai 27ae150435SJeff Kirsher #define TX_FIFO_LOW_THRESHOLD ((u32)1600) 28ae150435SJeff Kirsher #define SMSC911X_EEPROM_SIZE ((u32)128) 29ae150435SJeff Kirsher #define USE_DEBUG 0 30ae150435SJeff Kirsher 31ae150435SJeff Kirsher /* This is the maximum number of packets to be received every 32ae150435SJeff Kirsher * NAPI poll */ 33ae150435SJeff Kirsher #define SMSC_NAPI_WEIGHT 16 34ae150435SJeff Kirsher 35ae150435SJeff Kirsher /* implements a PHY loopback test at initialisation time, to ensure a packet 36ae150435SJeff Kirsher * can be successfully looped back */ 37ae150435SJeff Kirsher #define USE_PHY_WORK_AROUND 38ae150435SJeff Kirsher 39ae150435SJeff Kirsher #if USE_DEBUG >= 1 40ae150435SJeff Kirsher #define SMSC_WARN(pdata, nlevel, fmt, args...) \ 41ae150435SJeff Kirsher netif_warn(pdata, nlevel, (pdata)->dev, \ 42ae150435SJeff Kirsher "%s: " fmt "\n", __func__, ##args) 43ae150435SJeff Kirsher #else 44ae150435SJeff Kirsher #define SMSC_WARN(pdata, nlevel, fmt, args...) \ 45ae150435SJeff Kirsher no_printk(fmt "\n", ##args) 46ae150435SJeff Kirsher #endif 47ae150435SJeff Kirsher 48ae150435SJeff Kirsher #if USE_DEBUG >= 2 49ae150435SJeff Kirsher #define SMSC_TRACE(pdata, nlevel, fmt, args...) \ 50ae150435SJeff Kirsher netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args) 51ae150435SJeff Kirsher #else 52ae150435SJeff Kirsher #define SMSC_TRACE(pdata, nlevel, fmt, args...) \ 53ae150435SJeff Kirsher no_printk(fmt "\n", ##args) 54ae150435SJeff Kirsher #endif 55ae150435SJeff Kirsher 56ae150435SJeff Kirsher #ifdef CONFIG_DEBUG_SPINLOCK 57ae150435SJeff Kirsher #define SMSC_ASSERT_MAC_LOCK(pdata) \ 5897eeebeaSLance Roy lockdep_assert_held(&pdata->mac_lock) 59ae150435SJeff Kirsher #else 60ae150435SJeff Kirsher #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0) 61ae150435SJeff Kirsher #endif /* CONFIG_DEBUG_SPINLOCK */ 62ae150435SJeff Kirsher 63ae150435SJeff Kirsher /* SMSC911x registers and bitfields */ 64ae150435SJeff Kirsher #define RX_DATA_FIFO 0x00 65ae150435SJeff Kirsher 66ae150435SJeff Kirsher #define TX_DATA_FIFO 0x20 67ae150435SJeff Kirsher #define TX_CMD_A_ON_COMP_ 0x80000000 68ae150435SJeff Kirsher #define TX_CMD_A_BUF_END_ALGN_ 0x03000000 69ae150435SJeff Kirsher #define TX_CMD_A_4_BYTE_ALGN_ 0x00000000 70ae150435SJeff Kirsher #define TX_CMD_A_16_BYTE_ALGN_ 0x01000000 71ae150435SJeff Kirsher #define TX_CMD_A_32_BYTE_ALGN_ 0x02000000 72ae150435SJeff Kirsher #define TX_CMD_A_DATA_OFFSET_ 0x001F0000 73ae150435SJeff Kirsher #define TX_CMD_A_FIRST_SEG_ 0x00002000 74ae150435SJeff Kirsher #define TX_CMD_A_LAST_SEG_ 0x00001000 75ae150435SJeff Kirsher #define TX_CMD_A_BUF_SIZE_ 0x000007FF 76ae150435SJeff Kirsher #define TX_CMD_B_PKT_TAG_ 0xFFFF0000 77ae150435SJeff Kirsher #define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000 78ae150435SJeff Kirsher #define TX_CMD_B_DISABLE_PADDING_ 0x00001000 79ae150435SJeff Kirsher #define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF 80ae150435SJeff Kirsher 81ae150435SJeff Kirsher #define RX_STATUS_FIFO 0x40 82ae150435SJeff Kirsher #define RX_STS_ES_ 0x00008000 83ae150435SJeff Kirsher #define RX_STS_LENGTH_ERR_ 0x00001000 84ae150435SJeff Kirsher #define RX_STS_MCAST_ 0x00000400 85ae150435SJeff Kirsher #define RX_STS_FRAME_TYPE_ 0x00000020 86ae150435SJeff Kirsher #define RX_STS_CRC_ERR_ 0x00000002 87ae150435SJeff Kirsher 88ae150435SJeff Kirsher #define RX_STATUS_FIFO_PEEK 0x44 89ae150435SJeff Kirsher 90ae150435SJeff Kirsher #define TX_STATUS_FIFO 0x48 91ae150435SJeff Kirsher #define TX_STS_ES_ 0x00008000 92ae150435SJeff Kirsher #define TX_STS_LOST_CARRIER_ 0x00000800 93ae150435SJeff Kirsher #define TX_STS_NO_CARRIER_ 0x00000400 94ae150435SJeff Kirsher #define TX_STS_LATE_COL_ 0x00000200 95ae150435SJeff Kirsher #define TX_STS_EXCESS_COL_ 0x00000100 96ae150435SJeff Kirsher 97ae150435SJeff Kirsher #define TX_STATUS_FIFO_PEEK 0x4C 98ae150435SJeff Kirsher 99ae150435SJeff Kirsher #define ID_REV 0x50 100ae150435SJeff Kirsher #define ID_REV_CHIP_ID_ 0xFFFF0000 101ae150435SJeff Kirsher #define ID_REV_REV_ID_ 0x0000FFFF 102ae150435SJeff Kirsher 103ae150435SJeff Kirsher #define INT_CFG 0x54 104ae150435SJeff Kirsher #define INT_CFG_INT_DEAS_ 0xFF000000 105ae150435SJeff Kirsher #define INT_CFG_INT_DEAS_CLR_ 0x00004000 106ae150435SJeff Kirsher #define INT_CFG_INT_DEAS_STS_ 0x00002000 107ae150435SJeff Kirsher #define INT_CFG_IRQ_INT_ 0x00001000 108ae150435SJeff Kirsher #define INT_CFG_IRQ_EN_ 0x00000100 109ae150435SJeff Kirsher #define INT_CFG_IRQ_POL_ 0x00000010 110ae150435SJeff Kirsher #define INT_CFG_IRQ_TYPE_ 0x00000001 111ae150435SJeff Kirsher 112ae150435SJeff Kirsher #define INT_STS 0x58 113ae150435SJeff Kirsher #define INT_STS_SW_INT_ 0x80000000 114ae150435SJeff Kirsher #define INT_STS_TXSTOP_INT_ 0x02000000 115ae150435SJeff Kirsher #define INT_STS_RXSTOP_INT_ 0x01000000 116ae150435SJeff Kirsher #define INT_STS_RXDFH_INT_ 0x00800000 117ae150435SJeff Kirsher #define INT_STS_RXDF_INT_ 0x00400000 118ae150435SJeff Kirsher #define INT_STS_TX_IOC_ 0x00200000 119ae150435SJeff Kirsher #define INT_STS_RXD_INT_ 0x00100000 120ae150435SJeff Kirsher #define INT_STS_GPT_INT_ 0x00080000 121ae150435SJeff Kirsher #define INT_STS_PHY_INT_ 0x00040000 122ae150435SJeff Kirsher #define INT_STS_PME_INT_ 0x00020000 123ae150435SJeff Kirsher #define INT_STS_TXSO_ 0x00010000 124ae150435SJeff Kirsher #define INT_STS_RWT_ 0x00008000 125ae150435SJeff Kirsher #define INT_STS_RXE_ 0x00004000 126ae150435SJeff Kirsher #define INT_STS_TXE_ 0x00002000 127ae150435SJeff Kirsher #define INT_STS_TDFU_ 0x00000800 128ae150435SJeff Kirsher #define INT_STS_TDFO_ 0x00000400 129ae150435SJeff Kirsher #define INT_STS_TDFA_ 0x00000200 130ae150435SJeff Kirsher #define INT_STS_TSFF_ 0x00000100 131ae150435SJeff Kirsher #define INT_STS_TSFL_ 0x00000080 132ae150435SJeff Kirsher #define INT_STS_RXDF_ 0x00000040 133ae150435SJeff Kirsher #define INT_STS_RDFL_ 0x00000020 134ae150435SJeff Kirsher #define INT_STS_RSFF_ 0x00000010 135ae150435SJeff Kirsher #define INT_STS_RSFL_ 0x00000008 136ae150435SJeff Kirsher #define INT_STS_GPIO2_INT_ 0x00000004 137ae150435SJeff Kirsher #define INT_STS_GPIO1_INT_ 0x00000002 138ae150435SJeff Kirsher #define INT_STS_GPIO0_INT_ 0x00000001 139ae150435SJeff Kirsher 140ae150435SJeff Kirsher #define INT_EN 0x5C 141ae150435SJeff Kirsher #define INT_EN_SW_INT_EN_ 0x80000000 142ae150435SJeff Kirsher #define INT_EN_TXSTOP_INT_EN_ 0x02000000 143ae150435SJeff Kirsher #define INT_EN_RXSTOP_INT_EN_ 0x01000000 144ae150435SJeff Kirsher #define INT_EN_RXDFH_INT_EN_ 0x00800000 145ae150435SJeff Kirsher #define INT_EN_TIOC_INT_EN_ 0x00200000 146ae150435SJeff Kirsher #define INT_EN_RXD_INT_EN_ 0x00100000 147ae150435SJeff Kirsher #define INT_EN_GPT_INT_EN_ 0x00080000 148ae150435SJeff Kirsher #define INT_EN_PHY_INT_EN_ 0x00040000 149ae150435SJeff Kirsher #define INT_EN_PME_INT_EN_ 0x00020000 150ae150435SJeff Kirsher #define INT_EN_TXSO_EN_ 0x00010000 151ae150435SJeff Kirsher #define INT_EN_RWT_EN_ 0x00008000 152ae150435SJeff Kirsher #define INT_EN_RXE_EN_ 0x00004000 153ae150435SJeff Kirsher #define INT_EN_TXE_EN_ 0x00002000 154ae150435SJeff Kirsher #define INT_EN_TDFU_EN_ 0x00000800 155ae150435SJeff Kirsher #define INT_EN_TDFO_EN_ 0x00000400 156ae150435SJeff Kirsher #define INT_EN_TDFA_EN_ 0x00000200 157ae150435SJeff Kirsher #define INT_EN_TSFF_EN_ 0x00000100 158ae150435SJeff Kirsher #define INT_EN_TSFL_EN_ 0x00000080 159ae150435SJeff Kirsher #define INT_EN_RXDF_EN_ 0x00000040 160ae150435SJeff Kirsher #define INT_EN_RDFL_EN_ 0x00000020 161ae150435SJeff Kirsher #define INT_EN_RSFF_EN_ 0x00000010 162ae150435SJeff Kirsher #define INT_EN_RSFL_EN_ 0x00000008 163ae150435SJeff Kirsher #define INT_EN_GPIO2_INT_ 0x00000004 164ae150435SJeff Kirsher #define INT_EN_GPIO1_INT_ 0x00000002 165ae150435SJeff Kirsher #define INT_EN_GPIO0_INT_ 0x00000001 166ae150435SJeff Kirsher 167ae150435SJeff Kirsher #define BYTE_TEST 0x64 168ae150435SJeff Kirsher 169ae150435SJeff Kirsher #define FIFO_INT 0x68 170ae150435SJeff Kirsher #define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000 171ae150435SJeff Kirsher #define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000 172ae150435SJeff Kirsher #define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00 173ae150435SJeff Kirsher #define FIFO_INT_RX_STS_LEVEL_ 0x000000FF 174ae150435SJeff Kirsher 175ae150435SJeff Kirsher #define RX_CFG 0x6C 176ae150435SJeff Kirsher #define RX_CFG_RX_END_ALGN_ 0xC0000000 177ae150435SJeff Kirsher #define RX_CFG_RX_END_ALGN4_ 0x00000000 178ae150435SJeff Kirsher #define RX_CFG_RX_END_ALGN16_ 0x40000000 179ae150435SJeff Kirsher #define RX_CFG_RX_END_ALGN32_ 0x80000000 180ae150435SJeff Kirsher #define RX_CFG_RX_DMA_CNT_ 0x0FFF0000 181ae150435SJeff Kirsher #define RX_CFG_RX_DUMP_ 0x00008000 182ae150435SJeff Kirsher #define RX_CFG_RXDOFF_ 0x00001F00 183ae150435SJeff Kirsher 184ae150435SJeff Kirsher #define TX_CFG 0x70 185ae150435SJeff Kirsher #define TX_CFG_TXS_DUMP_ 0x00008000 186ae150435SJeff Kirsher #define TX_CFG_TXD_DUMP_ 0x00004000 187ae150435SJeff Kirsher #define TX_CFG_TXSAO_ 0x00000004 188ae150435SJeff Kirsher #define TX_CFG_TX_ON_ 0x00000002 189ae150435SJeff Kirsher #define TX_CFG_STOP_TX_ 0x00000001 190ae150435SJeff Kirsher 191ae150435SJeff Kirsher #define HW_CFG 0x74 192ae150435SJeff Kirsher #define HW_CFG_TTM_ 0x00200000 193ae150435SJeff Kirsher #define HW_CFG_SF_ 0x00100000 194ae150435SJeff Kirsher #define HW_CFG_TX_FIF_SZ_ 0x000F0000 195ae150435SJeff Kirsher #define HW_CFG_TR_ 0x00003000 196ae150435SJeff Kirsher #define HW_CFG_SRST_ 0x00000001 197ae150435SJeff Kirsher 198ae150435SJeff Kirsher /* only available on 115/117 */ 199ae150435SJeff Kirsher #define HW_CFG_PHY_CLK_SEL_ 0x00000060 200ae150435SJeff Kirsher #define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000 201ae150435SJeff Kirsher #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020 202ae150435SJeff Kirsher #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040 203ae150435SJeff Kirsher #define HW_CFG_SMI_SEL_ 0x00000010 204ae150435SJeff Kirsher #define HW_CFG_EXT_PHY_DET_ 0x00000008 205ae150435SJeff Kirsher #define HW_CFG_EXT_PHY_EN_ 0x00000004 206ae150435SJeff Kirsher #define HW_CFG_SRST_TO_ 0x00000002 207ae150435SJeff Kirsher 208ae150435SJeff Kirsher /* only available on 116/118 */ 209ae150435SJeff Kirsher #define HW_CFG_32_16_BIT_MODE_ 0x00000004 210ae150435SJeff Kirsher 211ae150435SJeff Kirsher #define RX_DP_CTRL 0x78 212ae150435SJeff Kirsher #define RX_DP_CTRL_RX_FFWD_ 0x80000000 213ae150435SJeff Kirsher 214ae150435SJeff Kirsher #define RX_FIFO_INF 0x7C 215ae150435SJeff Kirsher #define RX_FIFO_INF_RXSUSED_ 0x00FF0000 216ae150435SJeff Kirsher #define RX_FIFO_INF_RXDUSED_ 0x0000FFFF 217ae150435SJeff Kirsher 218ae150435SJeff Kirsher #define TX_FIFO_INF 0x80 219ae150435SJeff Kirsher #define TX_FIFO_INF_TSUSED_ 0x00FF0000 220ae150435SJeff Kirsher #define TX_FIFO_INF_TDFREE_ 0x0000FFFF 221ae150435SJeff Kirsher 222ae150435SJeff Kirsher #define PMT_CTRL 0x84 223ae150435SJeff Kirsher #define PMT_CTRL_PM_MODE_ 0x00003000 224ae150435SJeff Kirsher #define PMT_CTRL_PM_MODE_D0_ 0x00000000 225ae150435SJeff Kirsher #define PMT_CTRL_PM_MODE_D1_ 0x00001000 226ae150435SJeff Kirsher #define PMT_CTRL_PM_MODE_D2_ 0x00002000 227ae150435SJeff Kirsher #define PMT_CTRL_PM_MODE_D3_ 0x00003000 228ae150435SJeff Kirsher #define PMT_CTRL_PHY_RST_ 0x00000400 229ae150435SJeff Kirsher #define PMT_CTRL_WOL_EN_ 0x00000200 230ae150435SJeff Kirsher #define PMT_CTRL_ED_EN_ 0x00000100 231ae150435SJeff Kirsher #define PMT_CTRL_PME_TYPE_ 0x00000040 232ae150435SJeff Kirsher #define PMT_CTRL_WUPS_ 0x00000030 233ae150435SJeff Kirsher #define PMT_CTRL_WUPS_NOWAKE_ 0x00000000 234ae150435SJeff Kirsher #define PMT_CTRL_WUPS_ED_ 0x00000010 235ae150435SJeff Kirsher #define PMT_CTRL_WUPS_WOL_ 0x00000020 236ae150435SJeff Kirsher #define PMT_CTRL_WUPS_MULTI_ 0x00000030 237ae150435SJeff Kirsher #define PMT_CTRL_PME_IND_ 0x00000008 238ae150435SJeff Kirsher #define PMT_CTRL_PME_POL_ 0x00000004 239ae150435SJeff Kirsher #define PMT_CTRL_PME_EN_ 0x00000002 240ae150435SJeff Kirsher #define PMT_CTRL_READY_ 0x00000001 241ae150435SJeff Kirsher 242ae150435SJeff Kirsher #define GPIO_CFG 0x88 243ae150435SJeff Kirsher #define GPIO_CFG_LED3_EN_ 0x40000000 244ae150435SJeff Kirsher #define GPIO_CFG_LED2_EN_ 0x20000000 245ae150435SJeff Kirsher #define GPIO_CFG_LED1_EN_ 0x10000000 246ae150435SJeff Kirsher #define GPIO_CFG_GPIO2_INT_POL_ 0x04000000 247ae150435SJeff Kirsher #define GPIO_CFG_GPIO1_INT_POL_ 0x02000000 248ae150435SJeff Kirsher #define GPIO_CFG_GPIO0_INT_POL_ 0x01000000 249ae150435SJeff Kirsher #define GPIO_CFG_EEPR_EN_ 0x00700000 250ae150435SJeff Kirsher #define GPIO_CFG_GPIOBUF2_ 0x00040000 251ae150435SJeff Kirsher #define GPIO_CFG_GPIOBUF1_ 0x00020000 252ae150435SJeff Kirsher #define GPIO_CFG_GPIOBUF0_ 0x00010000 253ae150435SJeff Kirsher #define GPIO_CFG_GPIODIR2_ 0x00000400 254ae150435SJeff Kirsher #define GPIO_CFG_GPIODIR1_ 0x00000200 255ae150435SJeff Kirsher #define GPIO_CFG_GPIODIR0_ 0x00000100 256ae150435SJeff Kirsher #define GPIO_CFG_GPIOD4_ 0x00000020 257ae150435SJeff Kirsher #define GPIO_CFG_GPIOD3_ 0x00000010 258ae150435SJeff Kirsher #define GPIO_CFG_GPIOD2_ 0x00000004 259ae150435SJeff Kirsher #define GPIO_CFG_GPIOD1_ 0x00000002 260ae150435SJeff Kirsher #define GPIO_CFG_GPIOD0_ 0x00000001 261ae150435SJeff Kirsher 262ae150435SJeff Kirsher #define GPT_CFG 0x8C 263ae150435SJeff Kirsher #define GPT_CFG_TIMER_EN_ 0x20000000 264ae150435SJeff Kirsher #define GPT_CFG_GPT_LOAD_ 0x0000FFFF 265ae150435SJeff Kirsher 266ae150435SJeff Kirsher #define GPT_CNT 0x90 267ae150435SJeff Kirsher #define GPT_CNT_GPT_CNT_ 0x0000FFFF 268ae150435SJeff Kirsher 269ae150435SJeff Kirsher #define WORD_SWAP 0x98 270ae150435SJeff Kirsher 271ae150435SJeff Kirsher #define FREE_RUN 0x9C 272ae150435SJeff Kirsher 273ae150435SJeff Kirsher #define RX_DROP 0xA0 274ae150435SJeff Kirsher 275ae150435SJeff Kirsher #define MAC_CSR_CMD 0xA4 276ae150435SJeff Kirsher #define MAC_CSR_CMD_CSR_BUSY_ 0x80000000 277ae150435SJeff Kirsher #define MAC_CSR_CMD_R_NOT_W_ 0x40000000 278ae150435SJeff Kirsher #define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF 279ae150435SJeff Kirsher 280ae150435SJeff Kirsher #define MAC_CSR_DATA 0xA8 281ae150435SJeff Kirsher 282ae150435SJeff Kirsher #define AFC_CFG 0xAC 283ae150435SJeff Kirsher #define AFC_CFG_AFC_HI_ 0x00FF0000 284ae150435SJeff Kirsher #define AFC_CFG_AFC_LO_ 0x0000FF00 285ae150435SJeff Kirsher #define AFC_CFG_BACK_DUR_ 0x000000F0 286ae150435SJeff Kirsher #define AFC_CFG_FCMULT_ 0x00000008 287ae150435SJeff Kirsher #define AFC_CFG_FCBRD_ 0x00000004 288ae150435SJeff Kirsher #define AFC_CFG_FCADD_ 0x00000002 289ae150435SJeff Kirsher #define AFC_CFG_FCANY_ 0x00000001 290ae150435SJeff Kirsher 291ae150435SJeff Kirsher #define E2P_CMD 0xB0 292ae150435SJeff Kirsher #define E2P_CMD_EPC_BUSY_ 0x80000000 293ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_ 0x70000000 294ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_READ_ 0x00000000 295ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_EWDS_ 0x10000000 296ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_EWEN_ 0x20000000 297ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_WRITE_ 0x30000000 298ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_WRAL_ 0x40000000 299ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_ERASE_ 0x50000000 300ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_ERAL_ 0x60000000 301ae150435SJeff Kirsher #define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000 302ae150435SJeff Kirsher #define E2P_CMD_EPC_TIMEOUT_ 0x00000200 303ae150435SJeff Kirsher #define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100 304ae150435SJeff Kirsher #define E2P_CMD_EPC_ADDR_ 0x000000FF 305ae150435SJeff Kirsher 306ae150435SJeff Kirsher #define E2P_DATA 0xB4 307ae150435SJeff Kirsher #define E2P_DATA_EEPROM_DATA_ 0x000000FF 308ae150435SJeff Kirsher #define LAN_REGISTER_EXTENT 0x00000100 309ae150435SJeff Kirsher 310f6fec61eSDavid Cai #define RESET_CTL 0x1F8 311f6fec61eSDavid Cai #define RESET_CTL_DIGITAL_RST_ 0x00000001 312f6fec61eSDavid Cai 313ae150435SJeff Kirsher /* 314ae150435SJeff Kirsher * MAC Control and Status Register (Indirect Address) 315ae150435SJeff Kirsher * Offset (through the MAC_CSR CMD and DATA port) 316ae150435SJeff Kirsher */ 317ae150435SJeff Kirsher #define MAC_CR 0x01 318ae150435SJeff Kirsher #define MAC_CR_RXALL_ 0x80000000 319ae150435SJeff Kirsher #define MAC_CR_HBDIS_ 0x10000000 320ae150435SJeff Kirsher #define MAC_CR_RCVOWN_ 0x00800000 321ae150435SJeff Kirsher #define MAC_CR_LOOPBK_ 0x00200000 322ae150435SJeff Kirsher #define MAC_CR_FDPX_ 0x00100000 323ae150435SJeff Kirsher #define MAC_CR_MCPAS_ 0x00080000 324ae150435SJeff Kirsher #define MAC_CR_PRMS_ 0x00040000 325ae150435SJeff Kirsher #define MAC_CR_INVFILT_ 0x00020000 326ae150435SJeff Kirsher #define MAC_CR_PASSBAD_ 0x00010000 327ae150435SJeff Kirsher #define MAC_CR_HFILT_ 0x00008000 328ae150435SJeff Kirsher #define MAC_CR_HPFILT_ 0x00002000 329ae150435SJeff Kirsher #define MAC_CR_LCOLL_ 0x00001000 330ae150435SJeff Kirsher #define MAC_CR_BCAST_ 0x00000800 331ae150435SJeff Kirsher #define MAC_CR_DISRTY_ 0x00000400 332ae150435SJeff Kirsher #define MAC_CR_PADSTR_ 0x00000100 333ae150435SJeff Kirsher #define MAC_CR_BOLMT_MASK_ 0x000000C0 334ae150435SJeff Kirsher #define MAC_CR_DFCHK_ 0x00000020 335ae150435SJeff Kirsher #define MAC_CR_TXEN_ 0x00000008 336ae150435SJeff Kirsher #define MAC_CR_RXEN_ 0x00000004 337ae150435SJeff Kirsher 338ae150435SJeff Kirsher #define ADDRH 0x02 339ae150435SJeff Kirsher 340ae150435SJeff Kirsher #define ADDRL 0x03 341ae150435SJeff Kirsher 342ae150435SJeff Kirsher #define HASHH 0x04 343ae150435SJeff Kirsher 344ae150435SJeff Kirsher #define HASHL 0x05 345ae150435SJeff Kirsher 346ae150435SJeff Kirsher #define MII_ACC 0x06 347ae150435SJeff Kirsher #define MII_ACC_PHY_ADDR_ 0x0000F800 348ae150435SJeff Kirsher #define MII_ACC_MIIRINDA_ 0x000007C0 349ae150435SJeff Kirsher #define MII_ACC_MII_WRITE_ 0x00000002 350ae150435SJeff Kirsher #define MII_ACC_MII_BUSY_ 0x00000001 351ae150435SJeff Kirsher 352ae150435SJeff Kirsher #define MII_DATA 0x07 353ae150435SJeff Kirsher 354ae150435SJeff Kirsher #define FLOW 0x08 355ae150435SJeff Kirsher #define FLOW_FCPT_ 0xFFFF0000 356ae150435SJeff Kirsher #define FLOW_FCPASS_ 0x00000004 357ae150435SJeff Kirsher #define FLOW_FCEN_ 0x00000002 358ae150435SJeff Kirsher #define FLOW_FCBSY_ 0x00000001 359ae150435SJeff Kirsher 360ae150435SJeff Kirsher #define VLAN1 0x09 361ae150435SJeff Kirsher 362ae150435SJeff Kirsher #define VLAN2 0x0A 363ae150435SJeff Kirsher 364ae150435SJeff Kirsher #define WUFF 0x0B 365ae150435SJeff Kirsher 366ae150435SJeff Kirsher #define WUCSR 0x0C 367ae150435SJeff Kirsher #define WUCSR_GUE_ 0x00000200 368ae150435SJeff Kirsher #define WUCSR_WUFR_ 0x00000040 369ae150435SJeff Kirsher #define WUCSR_MPR_ 0x00000020 370ae150435SJeff Kirsher #define WUCSR_WAKE_EN_ 0x00000004 371ae150435SJeff Kirsher #define WUCSR_MPEN_ 0x00000002 372ae150435SJeff Kirsher 373ae150435SJeff Kirsher /* 374ae150435SJeff Kirsher * Phy definitions (vendor-specific) 375ae150435SJeff Kirsher */ 376ae150435SJeff Kirsher #define LAN9118_PHY_ID 0x00C0001C 377ae150435SJeff Kirsher 378ae150435SJeff Kirsher #define MII_INTSTS 0x1D 379ae150435SJeff Kirsher 380ae150435SJeff Kirsher #define MII_INTMSK 0x1E 381ae150435SJeff Kirsher #define PHY_INTMSK_AN_RCV_ (1 << 1) 382ae150435SJeff Kirsher #define PHY_INTMSK_PDFAULT_ (1 << 2) 383ae150435SJeff Kirsher #define PHY_INTMSK_AN_ACK_ (1 << 3) 384ae150435SJeff Kirsher #define PHY_INTMSK_LNKDOWN_ (1 << 4) 385ae150435SJeff Kirsher #define PHY_INTMSK_RFAULT_ (1 << 5) 386ae150435SJeff Kirsher #define PHY_INTMSK_AN_COMP_ (1 << 6) 387ae150435SJeff Kirsher #define PHY_INTMSK_ENERGYON_ (1 << 7) 388ae150435SJeff Kirsher #define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \ 389ae150435SJeff Kirsher PHY_INTMSK_AN_COMP_ | \ 390ae150435SJeff Kirsher PHY_INTMSK_RFAULT_ | \ 391ae150435SJeff Kirsher PHY_INTMSK_LNKDOWN_) 392ae150435SJeff Kirsher 393ae150435SJeff Kirsher #define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \ 394ae150435SJeff Kirsher ADVERTISE_PAUSE_ASYM) 395ae150435SJeff Kirsher 396ae150435SJeff Kirsher #define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \ 397ae150435SJeff Kirsher LPA_PAUSE_ASYM) 398ae150435SJeff Kirsher 399ae150435SJeff Kirsher /* 400ae150435SJeff Kirsher * Provide hooks to let the arch add to the initialisation procedure 401ae150435SJeff Kirsher * and to override the source of the MAC address. 402ae150435SJeff Kirsher */ 403ae150435SJeff Kirsher #define SMSC_INITIALIZE() do {} while (0) 404ae150435SJeff Kirsher #define smsc_get_mac(dev) smsc911x_read_mac_address((dev)) 405ae150435SJeff Kirsher 406ae150435SJeff Kirsher #ifdef CONFIG_SMSC911X_ARCH_HOOKS 407ae150435SJeff Kirsher #include <asm/smsc911x.h> 408ae150435SJeff Kirsher #endif 409ae150435SJeff Kirsher 41043c6759eSJavier Martinez Canillas #include <linux/smscphy.h> 41143c6759eSJavier Martinez Canillas 412ae150435SJeff Kirsher #endif /* __SMSC911X_H__ */ 413