1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b501fd7bSArnd Bergmann /* 3b501fd7bSArnd Bergmann * Common address map definitions 4b501fd7bSArnd Bergmann */ 5b501fd7bSArnd Bergmann 6b501fd7bSArnd Bergmann #ifndef __ASM_MACH_ADDR_MAP_H 7b501fd7bSArnd Bergmann #define __ASM_MACH_ADDR_MAP_H 8b501fd7bSArnd Bergmann 9b501fd7bSArnd Bergmann /* APB - Application Subsystem Peripheral Bus 10b501fd7bSArnd Bergmann * 11b501fd7bSArnd Bergmann * NOTE: the DMA controller registers are actually on the AXI fabric #1 12b501fd7bSArnd Bergmann * slave port to AHB/APB bridge, due to its close relationship to those 13b501fd7bSArnd Bergmann * peripherals on APB, let's count it into the ABP mapping area. 14b501fd7bSArnd Bergmann */ 15b501fd7bSArnd Bergmann #define APB_PHYS_BASE 0xd4000000 16b501fd7bSArnd Bergmann #define APB_VIRT_BASE IOMEM(0xfe000000) 17b501fd7bSArnd Bergmann #define APB_PHYS_SIZE 0x00200000 18b501fd7bSArnd Bergmann 19b501fd7bSArnd Bergmann #define AXI_PHYS_BASE 0xd4200000 20b501fd7bSArnd Bergmann #define AXI_VIRT_BASE IOMEM(0xfe200000) 21b501fd7bSArnd Bergmann #define AXI_PHYS_SIZE 0x00200000 22b501fd7bSArnd Bergmann 23*e69fd509SLubomir Rintel #define PGU_PHYS_BASE 0xe0000000 24*e69fd509SLubomir Rintel #define PGU_VIRT_BASE IOMEM(0xfe400000) 25*e69fd509SLubomir Rintel #define PGU_PHYS_SIZE 0x00100000 26*e69fd509SLubomir Rintel 27b501fd7bSArnd Bergmann /* Static Memory Controller - Chip Select 0 and 1 */ 28b501fd7bSArnd Bergmann #define SMC_CS0_PHYS_BASE 0x80000000 29b501fd7bSArnd Bergmann #define SMC_CS0_PHYS_SIZE 0x10000000 30b501fd7bSArnd Bergmann #define SMC_CS1_PHYS_BASE 0x90000000 31b501fd7bSArnd Bergmann #define SMC_CS1_PHYS_SIZE 0x10000000 32b501fd7bSArnd Bergmann 33b501fd7bSArnd Bergmann #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) 34b501fd7bSArnd Bergmann #define APMU_REG(x) (APMU_VIRT_BASE + (x)) 35b501fd7bSArnd Bergmann 36b501fd7bSArnd Bergmann #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) 37b501fd7bSArnd Bergmann #define APBC_REG(x) (APBC_VIRT_BASE + (x)) 38b501fd7bSArnd Bergmann 39b501fd7bSArnd Bergmann #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) 40b501fd7bSArnd Bergmann #define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) 41b501fd7bSArnd Bergmann 42b501fd7bSArnd Bergmann #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) 43b501fd7bSArnd Bergmann #define CIU_REG(x) (CIU_VIRT_BASE + (x)) 44b501fd7bSArnd Bergmann 45*e69fd509SLubomir Rintel #define SCU_VIRT_BASE (PGU_VIRT_BASE) 46*e69fd509SLubomir Rintel #define SCU_REG(x) (SCU_VIRT_BASE + (x)) 47*e69fd509SLubomir Rintel 48b501fd7bSArnd Bergmann #endif /* __ASM_MACH_ADDR_MAP_H */ 49