| /freebsd/sys/dev/age/ |
| H A D | if_agereg.h | 36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | snps,dw-wdt.yaml | 70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
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| /freebsd/lib/libc/locale/ |
| H A D | utf8.5 | 47 so 0x00-0x7f refer to the
57 [0x00000000 - 0x0000007f] [00000000.0bbbbbbb] -> 0bbbbbbb
58 [0x00000080 - 0x000007ff] [00000bbb.bbbbbbbb] -> 110bbbbb, 10bbbbbb
59 [0x00000800 - 0x0000ffff] [bbbbbbbb.bbbbbbbb] ->
61 [0x00010000 - 0x001fffff] [00000000.000bbbbb.bbbbbbbb.bbbbbbbb] ->
63 [0x00200000 - 0x03ffffff] [000000bb.bbbbbbbb.bbbbbbbb.bbbbbbbb] ->
65 [0x04000000 - 0x7fffffff] [0bbbbbbb.bbbbbbbb.bbbbbbbb.bbbbbbbb] ->
70 0x00; 0xC0 0x80; 0xE0 0x80 0x80) the shortest representation is always
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| /freebsd/sys/powerpc/powermac/ |
| H A D | ata_macio.c | 58 #define ATA_MACIO_ALTOFFSET 0x160
68 #define USE_DBDMA_IRQ 0
73 #define ATA_MACIO_TIMINGREG 0x200
89 { 600, 180 }, /* PIO 0 */
97 { 480, 240 }, /* WDMA 0 */
103 { 120, 180 }, /* UDMA 0 */
160 if (strcmp(type, "ata") != 0 && in ata_macio_probe()
161 strcmp(type, "ide") != 0) in ata_macio_probe()
167 if (strcmp(name,"ata-4") == 0) { in ata_macio_probe()
192 rid = 0; in ata_macio_attach()
[all …]
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| /freebsd/contrib/ntp/libntp/lib/isc/ |
| H A D | random.c | 51 pid = ((pid << 16) & 0xffff0000) | ((pid >> 16) & 0xffff); in initialize_rand()
85 #if RAND_MAX >= 0xfffff in isc_random_get()
87 *val = ((rand() >> 4) & 0xffff) | ((rand() << 12) & 0xffff0000); in isc_random_get()
88 #elif RAND_MAX >= 0x7fff in isc_random_get()
90 *val = ((rand() >> 4) & 0x000007ff) | ((rand() << 7) & 0x003ff800) | in isc_random_get()
91 ((rand() << 18) & 0xffc00000); in isc_random_get()
104 REQUIRE(jitter < max || (jitter == 0 && max == 0)); in isc_random_jitter()
106 if (jitter == 0) in isc_random_jitter()
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| /freebsd/sys/dev/sound/pci/ |
| H A D | emuxkireg.h | 50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
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| /freebsd/sys/dev/usb/controller/ |
| H A D | dwc_otgreg.h | 32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
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| /freebsd/sys/dev/vr/ |
| H A D | if_vrreg.h | 39 #define VR_PAR0 0x00 /* node address 0 to 4 */
40 #define VR_PAR1 0x04 /* node address 2 to 6 */
41 #define VR_RXCFG 0x06 /* receiver config register */
42 #define VR_TXCFG 0x07 /* transmit config register */
43 #define VR_CR0 0x08 /* command register 0 */
44 #define VR_CR1 0x09 /* command register 1 */
45 #define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */
46 #define VR_ISR 0x0C /* interrupt/status register */
47 #define VR_IMR 0x0E /* interrupt mask register */
48 #define VR_MAR0 0x10 /* multicast hash 0 */
[all …]
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| /freebsd/sys/dev/my/ |
| H A D | if_myreg.h | 33 #define MY_PAR0 0x0 /* physical address 0-3 */
34 #define MY_PAR1 0x04 /* physical address 4-5 */
35 #define MY_MAR0 0x08 /* multicast address 0-3 */
36 #define MY_MAR1 0x0C /* multicast address 4-7 */
37 #define MY_FAR0 0x10 /* flow-control address 0-3 */
38 #define MY_FAR1 0x14 /* flow-control address 4-5 */
39 #define MY_TCRRCR 0x18 /* receive & transmit configuration */
40 #define MY_BCR 0x1C /* bus command */
41 #define MY_TXPDR 0x20 /* transmit polling demand */
42 #define MY_RXPDR 0x24 /* receive polling demand */
[all …]
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_an_lt_wrapper_regs.h | 60 /* [0x0] AN LT wrapper Version */
62 /* [0x4] AN LT general configuration */
67 /* [0x0] AN LT register file address */
69 /* [0x4] PCS register file data */
71 /* [0x8] AN LT control signals */
73 /* [0xc] AN LT status signals */
79 AL_ETH_AN_LT_UNIT_32_BIT = 0,
86 struct al_an_lt_wrapper_gen gen; /* [0x100] */
87 struct al_an_lt_wrapper_an_lt an_lt[3]; /* [0x140] */
98 #define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
[all …]
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| /freebsd/contrib/opencsd/decoder/source/i_dec/ |
| H A D | trc_idec_arminst.cpp | 48 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_direct_branch()
50 if ((inst & 0xfe000000) == 0xfa000000){ in inst_ARM_is_direct_branch()
53 is_direct_branch = 0; in inst_ARM_is_direct_branch()
55 } else if ((inst & 0x0e000000) == 0x0a000000) { in inst_ARM_is_direct_branch()
58 is_direct_branch = 0; in inst_ARM_is_direct_branch()
65 if ( ((inst & 0xf0000000) != 0xf0000000) && in inst_ARM_wfiwfe()
66 ((inst & 0x0ffffffe) == 0x0320f002) in inst_ARM_wfiwfe()
70 return 0; in inst_ARM_wfiwfe()
76 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_indirect_branch()
78 if ((inst & 0xfe500000) == 0xf8100000) { in inst_ARM_is_indirect_branch()
[all …]
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| /freebsd/contrib/nvi/ex/ |
| H A D | ex.h | 16 #define E_ADDR1 0x00000001 /* One address. */
17 #define E_ADDR2 0x00000002 /* Two addresses. */
18 #define E_ADDR2_ALL 0x00000004 /* Zero/two addresses; zero == all. */
19 #define E_ADDR2_NONE 0x00000008 /* Zero/two addresses; zero == none. */
20 #define E_ADDR_ZERO 0x00000010 /* 0 is a legal addr1. */
21 #define E_ADDR_ZERODEF 0x00000020 /* 0 is default addr1 of empty files. */
22 #define E_AUTOPRINT 0x00000040 /* Command always sets autoprint. */
23 #define E_CLRFLAG 0x00000080 /* Clear the print (#, l, p) flags. */
24 #define E_NEWSCREEN 0x00000100 /* Create a new screen. */
25 #define E_SECURE 0x00000200 /* Permission denied if O_SECURE set. */
[all …]
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9462_2p1_initvals.h | 63 {0x00000008, 0x00000000},
64 {0x00000030, 0x000e0085},
65 {0x00000034, 0x00000005},
66 {0x00000040, 0x00000000},
67 {0x00000044, 0x00000000},
68 {0x00000048, 0x00000008},
69 {0x0000004c, 0x00000010},
70 {0x00000050, 0x00000000},
71 {0x00001040, 0x002ffc0f},
72 {0x00001044, 0x002ffc0f},
[all …]
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| /freebsd/contrib/ncurses/ncurses/tinfo/ |
| H A D | obsolete.c | 67 char *result = 0; in _nc_strdup()
68 if (s != 0) { in _nc_strdup()
71 if (result != 0) { in _nc_strdup()
85 if (n != 0) { in _nc_memmove()
94 for (j = 0; j < n; j++) in _nc_memmove()
98 while (n-- != 0) in _nc_memmove()
110 int rc = 0; in _nc_conv_to_utf8()
112 if (source <= 0x0000007f) in _nc_conv_to_utf8()
114 else if (source <= 0x000007ff) in _nc_conv_to_utf8()
116 else if (source <= 0x0000ffff) in _nc_conv_to_utf8()
[all …]
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| /freebsd/sys/contrib/dev/athk/ath10k/ |
| H A D | rx_desc.h | 13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
57 * 0. The PPDU start status will only be valid when this bit
66 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
227 * ring 0. Field is filled in by the RX_DMA.
243 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
256 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
257 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
258 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
260 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
268 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
[all …]
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| H A D | hw.h | 23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
24 #define QCA988X_2_0_DEVICE_ID (0x003c)
25 #define QCA6164_2_1_DEVICE_ID (0x0041)
26 #define QCA6174_2_1_DEVICE_ID (0x003e)
27 #define QCA6174_3_2_DEVICE_ID (0x0042)
28 #define QCA99X0_2_0_DEVICE_ID (0x0040)
29 #define QCA9888_2_0_DEVICE_ID (0x0056)
30 #define QCA9984_1_0_DEVICE_ID (0x0046)
31 #define QCA9377_1_0_DEVICE_ID (0x0042)
32 #define QCA9887_1_0_DEVICE_ID (0x0050)
[all …]
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| /freebsd/sys/dev/ale/ |
| H A D | if_alereg.h | 36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5210/ |
| H A D | ar5210reg.h | 28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
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| /freebsd/sys/dev/alc/ |
| H A D | if_alcreg.h | 36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
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| /freebsd/sys/dev/dc/ |
| H A D | if_dcreg.h | 39 #define DC_BUSCTL 0x00 /* bus control */
40 #define DC_TXSTART 0x08 /* tx start demand */
41 #define DC_RXSTART 0x10 /* rx start demand */
42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
44 #define DC_ISR 0x28 /* interrupt status register */
45 #define DC_NETCFG 0x30 /* network config register */
46 #define DC_IMR 0x38 /* interrupt mask */
47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
[all …]
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| /freebsd/sys/contrib/dev/rtw89/ |
| H A D | rtw8852b.c | 22 {5, 341, grp_0}, /* ACH 0 */
26 {0, 0, grp_0}, /* ACH 4 */
27 {0, 0, grp_0}, /* ACH 5 */
28 {0, 0, grp_0}, /* ACH 6 */
29 {0, 0, grp_0}, /* ACH 7 */
32 {0,
[all...] |
| /freebsd/tools/test/iconv/ref/ |
| H A D | UTF-8 | 1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
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| /freebsd/sys/dev/cas/ |
| H A D | if_casreg.h | 42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
|