Lines Matching +full:0 +full:x000007ff
39 #define VR_PAR0 0x00 /* node address 0 to 4 */
40 #define VR_PAR1 0x04 /* node address 2 to 6 */
41 #define VR_RXCFG 0x06 /* receiver config register */
42 #define VR_TXCFG 0x07 /* transmit config register */
43 #define VR_CR0 0x08 /* command register 0 */
44 #define VR_CR1 0x09 /* command register 1 */
45 #define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */
46 #define VR_ISR 0x0C /* interrupt/status register */
47 #define VR_IMR 0x0E /* interrupt mask register */
48 #define VR_MAR0 0x10 /* multicast hash 0 */
49 #define VR_MAR1 0x14 /* multicast hash 1 */
50 #define VR_MCAM0 0x10
51 #define VR_MCAM1 0x11
52 #define VR_MCAM2 0x12
53 #define VR_MCAM3 0x13
54 #define VR_MCAM4 0x14
55 #define VR_MCAM5 0x15
56 #define VR_VCAM0 0x16
57 #define VR_VCAM1 0x17
58 #define VR_RXADDR 0x18 /* rx descriptor list start addr */
59 #define VR_TXADDR 0x1C /* tx descriptor list start addr */
60 #define VR_CURRXDESC0 0x20
61 #define VR_CURRXDESC1 0x24
62 #define VR_CURRXDESC2 0x28
63 #define VR_CURRXDESC3 0x2C
64 #define VR_NEXTRXDESC0 0x30
65 #define VR_NEXTRXDESC1 0x34
66 #define VR_NEXTRXDESC2 0x38
67 #define VR_NEXTRXDESC3 0x3C
68 #define VR_CURTXDESC0 0x40
69 #define VR_CURTXDESC1 0x44
70 #define VR_CURTXDESC2 0x48
71 #define VR_CURTXDESC3 0x4C
72 #define VR_NEXTTXDESC0 0x50
73 #define VR_NEXTTXDESC1 0x54
74 #define VR_NEXTTXDESC2 0x58
75 #define VR_NEXTTXDESC3 0x5C
76 #define VR_CURRXDMA 0x60 /* current RX DMA address */
77 #define VR_CURTXDMA 0x64 /* current TX DMA address */
78 #define VR_TALLYCNT 0x68 /* tally counter test register */
79 #define VR_PHYADDR 0x6C
80 #define VR_MIISTAT 0x6D
81 #define VR_BCR0 0x6E
82 #define VR_BCR1 0x6F
83 #define VR_MIICMD 0x70
84 #define VR_MIIADDR 0x71
85 #define VR_MIIDATA 0x72
86 #define VR_EECSR 0x74
87 #define VR_TEST 0x75
88 #define VR_GPIO 0x76
89 #define VR_CFGA 0x78
90 #define VR_CFGB 0x79
91 #define VR_CFGC 0x7A
92 #define VR_CFGD 0x7B
93 #define VR_MPA_CNT 0x7C
94 #define VR_CRC_CNT 0x7E
95 #define VR_MISC_CR0 0x80 /* VT6102, 8bits */
96 #define VR_MISC_CR1 0x81
97 #define VR_STICKHW 0x83
98 #define VR_MII_ISR 0x84
99 #define VR_MII_IMR 0x86
100 #define VR_CAMMASK 0x88 /* VT6105M, 32bits */
101 #define VR_CAMCTL 0x92 /* VT6105M, 8bits */
102 #define VR_CAMADDR 0x93 /* VT6105M, 8bits */
103 #define VR_FLOWCR0 0x98
104 #define VR_FLOWCR1 0x99
105 #define VR_PAUSETIMER 0x9A /* 16bit */
106 #define VR_WOLCR_SET 0xA0
107 #define VR_PWRCFG_SET 0xA1
108 #define VR_TESTREG_SET 0xA2
109 #define VR_WOLCFG_SET 0xA3
110 #define VR_WOLCR_CLR 0xA4
111 #define VR_PWRCFG_CLR 0xA5
112 #define VR_TESTREG_CLR 0xA6
113 #define VR_WOLCFG_CLR 0xA7
114 #define VR_PWRCSR_SET 0xA8
115 #define VR_PWRCSR1_SET 0xA9
116 #define VR_PWRCSR_CLR 0xAC
117 #define VR_PWRCSR1_CLR 0xAD
120 #define VR_MISCCR0_RXPAUSE 0x08
121 #define VR_MISCCR1_FORSRST 0x40
126 #define VR_RXCFG_RX_ERRPKTS 0x01
127 #define VR_RXCFG_RX_RUNT 0x02
128 #define VR_RXCFG_RX_MULTI 0x04
129 #define VR_RXCFG_RX_BROAD 0x08
130 #define VR_RXCFG_RX_PROMISC 0x10
131 #define VR_RXCFG_RX_THRESH 0xE0
133 #define VR_RXTHRESH_32BYTES 0x00
134 #define VR_RXTHRESH_64BYTES 0x20
135 #define VR_RXTHRESH_128BYTES 0x40
136 #define VR_RXTHRESH_256BYTES 0x60
137 #define VR_RXTHRESH_512BYTES 0x80
138 #define VR_RXTHRESH_768BYTES 0xA0
139 #define VR_RXTHRESH_1024BYTES 0xC0
140 #define VR_RXTHRESH_STORENFWD 0xE0
145 #define VR_TXCFG_TXTAGEN 0x01 /* 6105M */
146 #define VR_TXCFG_LOOPBKMODE 0x06
147 #define VR_TXCFG_BACKOFF 0x08
148 #define VR_TXCFG_RXTAGCTL 0x10 /* 6105M */
149 #define VR_TXCFG_TX_THRESH 0xE0
151 #define VR_TXTHRESH_32BYTES 0x00
152 #define VR_TXTHRESH_64BYTES 0x20
153 #define VR_TXTHRESH_128BYTES 0x40
154 #define VR_TXTHRESH_256BYTES 0x60
155 #define VR_TXTHRESH_512BYTES 0x80
156 #define VR_TXTHRESH_768BYTES 0xA0
157 #define VR_TXTHRESH_1024BYTES 0xC0
158 #define VR_TXTHRESH_STORENFWD 0xE0
165 #define VR_CR0_INIT 0x01
166 #define VR_CR0_START 0x02
167 #define VR_CR0_STOP 0x04
168 #define VR_CR0_RX_ON 0x08
169 #define VR_CR0_TX_ON 0x10
170 #define VR_CR0_TX_GO 0x20
171 #define VR_CR0_RX_GO 0x40
172 #define VR_CR0_RSVD 0x80
173 #define VR_CR1_RX_EARLY 0x01
174 #define VR_CR1_TX_EARLY 0x02
175 #define VR_CR1_FULLDUPLEX 0x04
176 #define VR_CR1_TX_NOPOLL 0x08
178 #define VR_CR1_RESET 0x80
183 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */
184 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */
185 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
186 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
187 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
188 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
189 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */
190 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
191 #define VR_ISR_RX_EARLY 0x0100 /* rx early */
192 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */
193 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */
194 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (6102) */
195 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
196 #define VR_ISR_RX_DROPPED 0x0800
197 #define VR_ISR_RX_NOBUF2 0x1000 /* Rx descriptor running up */
198 #define VR_ISR_TX_ABRT2 0x2000
199 #define VR_ISR_LINKSTAT2 0x4000
200 #define VR_ISR_MAGICPACKET 0x8000
210 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */
211 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */
212 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
213 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
214 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
215 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
216 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */
217 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
218 #define VR_IMR_RX_EARLY 0x0100 /* rx early */
219 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */
220 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
221 #define VR_IMR_RX_DROPPED 0x0800
222 #define VR_IMR_RX_NOBUF2 0x1000
223 #define VR_IMR_TX_ABRT2 0x2000
224 #define VR_IMR_LINKSTAT2 0x4000
225 #define VR_IMR_MAGICPACKET 0x8000
236 #define VR_MIISTAT_SPEED 0x01
237 #define VR_MIISTAT_LINKFAULT 0x02
238 #define VR_MIISTAT_MGTREADERR 0x04
239 #define VR_MIISTAT_MIIERR 0x08
240 #define VR_MIISTAT_PHYOPT 0x10
241 #define VR_MIISTAT_MDC_SPEED 0x20
242 #define VR_MIISTAT_RSVD 0x40
243 #define VR_MIISTAT_GPIO1POLL 0x80
248 #define VR_MIICMD_CLK 0x01
249 #define VR_MIICMD_DATAOUT 0x02
250 #define VR_MIICMD_DATAIN 0x04
251 #define VR_MIICMD_DIR 0x08
252 #define VR_MIICMD_DIRECTPGM 0x10
253 #define VR_MIICMD_WRITE_ENB 0x20
254 #define VR_MIICMD_READ_ENB 0x40
255 #define VR_MIICMD_AUTOPOLL 0x80
260 #define VR_EECSR_DATAIN 0x01 /* data out */
261 #define VR_EECSR_DATAOUT 0x02 /* data in */
262 #define VR_EECSR_CLK 0x04 /* clock */
263 #define VR_EECSR_CS 0x08 /* chip select */
264 #define VR_EECSR_DPM 0x10
265 #define VR_EECSR_LOAD 0x20
266 #define VR_EECSR_EMBP 0x40
267 #define VR_EECSR_EEPR 0x80
269 #define VR_EECMD_WRITE 0x140
270 #define VR_EECMD_READ 0x180
271 #define VR_EECMD_ERASE 0x1c0
276 #define VR_TEST_TEST0 0x01
277 #define VR_TEST_TEST1 0x02
278 #define VR_TEST_TEST2 0x04
279 #define VR_TEST_TSTUD 0x08
280 #define VR_TEST_TSTOV 0x10
281 #define VR_TEST_BKOFF 0x20
282 #define VR_TEST_FCOL 0x40
283 #define VR_TEST_HBDES 0x80
288 #define VR_CFG_GPIO2OUTENB 0x01
289 #define VR_CFG_GPIO2OUT 0x02 /* gen. purp. pin */
290 #define VR_CFG_GPIO2IN 0x04 /* gen. purp. pin */
291 #define VR_CFG_AUTOOPT 0x08 /* enable rx/tx autopoll */
292 #define VR_CFG_MIIOPT 0x10
293 #define VR_CFG_MMIENB 0x20 /* memory mapped mode enb */
294 #define VR_CFG_JUMPER 0x40 /* PHY and oper. mode select */
295 #define VR_CFG_EELOAD 0x80 /* enable EEPROM programming */
300 #define VR_CFG_LATMENB 0x01 /* larency timer effect enb. */
301 #define VR_CFG_MRREADWAIT 0x02
302 #define VR_CFG_MRWRITEWAIT 0x04
303 #define VR_CFG_RX_ARB 0x08
304 #define VR_CFG_TX_ARB 0x10
305 #define VR_CFG_READMULTI 0x20
306 #define VR_CFG_TX_PACE 0x40
307 #define VR_CFG_TX_QDIS 0x80
312 #define VR_CFG_ROMSEL0 0x01
313 #define VR_CFG_ROMSEL1 0x02
314 #define VR_CFG_ROMSEL2 0x04
315 #define VR_CFG_ROMTIMESEL 0x08
316 #define VR_CFG_RSVD0 0x10
317 #define VR_CFG_ROMDLY 0x20
318 #define VR_CFG_ROMOPT 0x40
319 #define VR_CFG_RSVD1 0x80
324 #define VR_CFG_BACKOFFOPT 0x01
325 #define VR_CFG_BACKOFFMOD 0x02
326 #define VR_CFG_CAPEFFECT 0x04
327 #define VR_CFG_BACKOFFRAND 0x08
328 #define VR_CFG_MAGICKPACKET 0x10
329 #define VR_CFG_PCIREADLINE 0x20
330 #define VR_CFG_DIAG 0x40
331 #define VR_CFG_GPIOEN 0x80
334 #define VR_STICKHW_DS0 0x01
335 #define VR_STICKHW_DS1 0x02
336 #define VR_STICKHW_WOL_ENB 0x04
337 #define VR_STICKHW_WOL_STS 0x08
338 #define VR_STICKHW_LEGWOL_ENB 0x80
343 #define VR_BCR0_DMA_LENGTH 0x07
345 #define VR_BCR0_DMA_32BYTES 0x00
346 #define VR_BCR0_DMA_64BYTES 0x01
347 #define VR_BCR0_DMA_128BYTES 0x02
348 #define VR_BCR0_DMA_256BYTES 0x03
349 #define VR_BCR0_DMA_512BYTES 0x04
350 #define VR_BCR0_DMA_1024BYTES 0x05
351 #define VR_BCR0_DMA_STORENFWD 0x07
353 #define VR_BCR0_RX_THRESH 0x38
355 #define VR_BCR0_RXTHRESHCFG 0x00
356 #define VR_BCR0_RXTHRESH64BYTES 0x08
357 #define VR_BCR0_RXTHRESH128BYTES 0x10
358 #define VR_BCR0_RXTHRESH256BYTES 0x18
359 #define VR_BCR0_RXTHRESH512BYTES 0x20
360 #define VR_BCR0_RXTHRESH1024BYTES 0x28
361 #define VR_BCR0_RXTHRESHSTORENFWD 0x38
362 #define VR_BCR0_EXTLED 0x40
363 #define VR_BCR0_MED2 0x80
368 #define VR_BCR1_POT0 0x01
369 #define VR_BCR1_POT1 0x02
370 #define VR_BCR1_POT2 0x04
371 #define VR_BCR1_TX_THRESH 0x38
372 #define VR_BCR1_TXTHRESHCFG 0x00
373 #define VR_BCR1_TXTHRESH64BYTES 0x08
374 #define VR_BCR1_TXTHRESH128BYTES 0x10
375 #define VR_BCR1_TXTHRESH256BYTES 0x18
376 #define VR_BCR1_TXTHRESH512BYTES 0x20
377 #define VR_BCR1_TXTHRESH1024BYTES 0x28
378 #define VR_BCR1_TXTHRESHSTORENFWD 0x38
379 #define VR_BCR1_VLANFILT_ENB 0x80 /* VT6105M */
384 #define VR_CAMCTL_ENA 0x01
385 #define VR_CAMCTL_VLAN 0x02
386 #define VR_CAMCTL_MCAST 0x00
387 #define VR_CAMCTL_WRITE 0x04
388 #define VR_CAMCTL_READ 0x08
396 #define VR_FLOWCR1_TXLO4 0x00
397 #define VR_FLOWCR1_TXLO8 0x40
398 #define VR_FLOWCR1_TXLO16 0x80
399 #define VR_FLOWCR1_TXLO24 0xC0
400 #define VR_FLOWCR1_TXHI24 0x00
401 #define VR_FLOWCR1_TXHI32 0x10
402 #define VR_FLOWCR1_TXHI48 0x20
403 #define VR_FLOWCR1_TXHI64 0x30
404 #define VR_FLOWCR1_XONXOFF 0x08
405 #define VR_FLOWCR1_TXPAUSE 0x04
406 #define VR_FLOWCR1_RXPAUSE 0x02
407 #define VR_FLOWCR1_HDX 0x01
412 #define VR_WOLCR_PATTERN0 0x01
413 #define VR_WOLCR_PATTERN1 0x02
414 #define VR_WOLCR_PATTERN2 0x04
415 #define VR_WOLCR_PATTERN3 0x08
416 #define VR_WOLCR_UCAST 0x10
417 #define VR_WOLCR_MAGIC 0x20
418 #define VR_WOLCR_LINKON 0x40
419 #define VR_WOLCR_LINKOFF 0x80
424 #define VR_PWRCFG_WOLEN 0x01
425 #define VR_PWRCFG_WOLSR 0x02
426 #define VR_PWRCFG_LEGACY_WOL 0x10
427 #define VR_PWRCFG_WOLTYPE_PULSE 0x20
428 #define VR_PWRCFG_SMIITIME 0x80
433 #define VR_WOLCFG_PATTERN_PAGE 0x04 /* VT6505 B0 */
434 #define VR_WOLCFG_SMIIOPT 0x04
435 #define VR_WOLCFG_SMIIACC 0x08
436 #define VR_WOLCFG_SAB 0x10
437 #define VR_WOLCFG_SAM 0x20
438 #define VR_WOLCFG_SFDX 0x40
439 #define VR_WOLCFG_PMEOVR 0x80
452 #define VR_RXSTAT_RXERR 0x00000001
453 #define VR_RXSTAT_CRCERR 0x00000002
454 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004
455 #define VR_RXSTAT_FIFOOFLOW 0x00000008
456 #define VR_RXSTAT_GIANT 0x00000010
457 #define VR_RXSTAT_RUNT 0x00000020
458 #define VR_RXSTAT_BUSERR 0x00000040
459 #define VR_RXSTAT_FRAG 0x00000040 /* 6105M */
460 #define VR_RXSTAT_BUFFERR 0x00000080
461 #define VR_RXSTAT_LASTFRAG 0x00000100
462 #define VR_RXSTAT_FIRSTFRAG 0x00000200
463 #define VR_RXSTAT_RLINK 0x00000400
464 #define VR_RXSTAT_RX_PHYS 0x00000800
465 #define VR_RXSTAT_RX_BROAD 0x00001000
466 #define VR_RXSTAT_RX_MULTI 0x00002000
467 #define VR_RXSTAT_RX_VIDHIT 0x00004000 /* 6105M */
468 #define VR_RXSTAT_RX_OK 0x00008000
469 #define VR_RXSTAT_RXLEN 0x07FF0000
470 #define VR_RXSTAT_RXLEN_EXT 0x78000000
471 #define VR_RXSTAT_OWN 0x80000000
479 #define VR_RXCTL_BUFLEN 0x000007FF
480 #define VR_RXCTL_BUFLEN_EXT 0x00007800
481 #define VR_RXCTL_CHAIN 0x00008000
482 #define VR_RXCTL_TAG 0x00010000
483 #define VR_RXCTL_UDP 0x00020000
484 #define VR_RXCTL_TCP 0x00040000
485 #define VR_RXCTL_IP 0x00080000
486 #define VR_RXCTL_TCPUDPOK 0x00100000
487 #define VR_RXCTL_IPOK 0x00200000
488 #define VR_RXCTL_SNAPTAG 0x00400000
489 #define VR_RXCTL_RXLERR 0x00800000 /* 6105M */
490 #define VR_RXCTL_RX_INTR 0x00800000
494 #define VR_TXSTAT_DEFER 0x00000001
495 #define VR_TXSTAT_UNDERRUN 0x00000002
496 #define VR_TXSTAT_COLLCNT 0x00000078
497 #define VR_TXSTAT_SQE 0x00000080
498 #define VR_TXSTAT_ABRT 0x00000100
499 #define VR_TXSTAT_LATECOLL 0x00000200
500 #define VR_TXSTAT_CARRLOST 0x00000400
501 #define VR_TXSTAT_UDF 0x00000800
502 #define VR_TXSTAT_TBUFF 0x00001000
503 #define VR_TXSTAT_BUSERR 0x00002000
504 #define VR_TXSTAT_JABTIMEO 0x00004000
505 #define VR_TXSTAT_ERRSUM 0x00008000
506 #define VR_TXSTAT_OWN 0x80000000
508 #define VR_TXCTL_BUFLEN 0x000007FF
509 #define VR_TXCTL_BUFLEN_EXT 0x00007800
510 #define VR_TXCTL_TLINK 0x00008000
511 #define VR_TXCTL_NOCRC 0x00010000
512 #define VR_TXCTL_INSERTTAG 0x00020000
513 #define VR_TXCTL_IPCSUM 0x00040000
514 #define VR_TXCTL_UDPCSUM 0x00080000
515 #define VR_TXCTL_TCPCSUM 0x00100000
516 #define VR_TXCTL_FIRSTFRAG 0x00200000
517 #define VR_TXCTL_LASTFRAG 0x00400000
518 #define VR_TXCTL_FINT 0x00800000
529 #define VR_PHYADDR_MASK 0x1f
536 #define VIA_VENDORID 0x1106
541 #define VIA_DEVICEID_RHINE 0x3043
542 #define VIA_DEVICEID_RHINE_II 0x6100
543 #define VIA_DEVICEID_RHINE_II_2 0x3065
544 #define VIA_DEVICEID_RHINE_III 0x3106
545 #define VIA_DEVICEID_RHINE_III_M 0x3053
550 #define DELTA_VENDORID 0x1500
555 #define DELTA_DEVICEID_RHINE_II 0x1320
560 #define ADDTRON_VENDORID 0x4033
565 #define ADDTRON_DEVICEID_RHINE_II 0x1320
571 #define REV_ID_VT3043_E 0x04
572 #define REV_ID_VT3071_A 0x20
573 #define REV_ID_VT3071_B 0x21
574 #define REV_ID_VT6102_A 0x40
575 #define REV_ID_VT6102_B 0x41
576 #define REV_ID_VT6102_C 0x42
577 #define REV_ID_VT6102_APOLLO 0x74
578 #define REV_ID_VT6105_A0 0x80
579 #define REV_ID_VT6105_B0 0x83
580 #define REV_ID_VT6105_LOM 0x8A
581 #define REV_ID_VT6107_A0 0x8C
582 #define REV_ID_VT6107_A1 0x8D
583 #define REV_ID_VT6105M_A0 0x90
584 #define REV_ID_VT6105M_B1 0x94
591 #define VR_PCI_VENDOR_ID 0x00
592 #define VR_PCI_DEVICE_ID 0x02
593 #define VR_PCI_COMMAND 0x04
594 #define VR_PCI_STATUS 0x06
595 #define VR_PCI_REVID 0x08
596 #define VR_PCI_CLASSCODE 0x09
597 #define VR_PCI_LATENCY_TIMER 0x0D
598 #define VR_PCI_HEADER_TYPE 0x0E
599 #define VR_PCI_LOIO 0x10
600 #define VR_PCI_LOMEM 0x14
601 #define VR_PCI_BIOSROM 0x30
602 #define VR_PCI_INTLINE 0x3C
603 #define VR_PCI_INTPIN 0x3D
604 #define VR_PCI_MINGNT 0x3E
605 #define VR_PCI_MINLAT 0x0F
606 #define VR_PCI_RESETOPT 0x48
607 #define VR_PCI_EEPROM_DATA 0x4C
608 #define VR_PCI_MODE0 0x50
609 #define VR_PCI_MODE2 0x52
610 #define VR_PCI_MODE3 0x53
612 #define VR_MODE2_PCEROPT 0x80 /* VT6102 only */
613 #define VR_MODE2_DISABT 0x40
614 #define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */
615 #define VR_MODE2_MODE10T 0x02
617 #define VR_MODE3_XONOPT 0x80
618 #define VR_MODE3_TPACEN 0x40
619 #define VR_MODE3_BACKOPT 0x20
620 #define VR_MODE3_DLTSEL 0x10
621 #define VR_MODE3_MIIDMY 0x08
622 #define VR_MODE3_MIION 0x04
625 #define VR_PCI_CAPID 0xDC /* 8 bits */
626 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */
627 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
628 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
630 #define VR_PSTATE_MASK 0x0003
631 #define VR_PSTATE_D0 0x0000
632 #define VR_PSTATE_D1 0x0002
633 #define VR_PSTATE_D2 0x0002
634 #define VR_PSTATE_D3 0x0003
635 #define VR_PME_EN 0x0010
636 #define VR_PME_STATUS 0x8000
647 #define VR_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff)
722 #define VR_F_RESTART 0x0001 /* Restart unit on next tick */
723 #define VR_F_TXPAUSE 0x0010
724 #define VR_F_SUSPENDED 0x2000
725 #define VR_F_DETACHED 0x4000
726 #define VR_F_LINK 0x8000
762 #define VR_MCAST_CAM 0