| 9515af58 | 13-Jul-2026 |
Li Ming <ming.li@zohomail.com> |
cxl/test: Rework cxl_type2_mem_init() to use cxl_mock_platform_device_add()
cxl_type2_mem_init() is used to set up mock CXL type2 memory device for cxl testing, it introduces a known bug fixed by th
cxl/test: Rework cxl_type2_mem_init() to use cxl_mock_platform_device_add()
cxl_type2_mem_init() is used to set up mock CXL type2 memory device for cxl testing, it introduces a known bug fixed by the following commit:
commit d90f236f8b9e ("cxl/test: Update mock dev array before calling platform_device_add()")
Mock CXL devices require updating the mock device array prior to platform_device_add(), otherwise, the CXL subsystem could fail to recognize the newly added mock device. Switch to cxl_mock_platform_device_add() helper to resolve this ordering issue.
Besides, this patch also includes two minor changes. 1. Preserve the original error code returned by cxl_mock_platform_device_add(), rather than unconditionally overriding it with -ENOMEM. 2. Drop redundant NULL check before platform_device_unregister(), as the function internally handles NULL pointer.
Fixes: 6b2e585142e6 ("cxl/test: Add hierarchy enumeration support for type2 device") Signed-off-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20260713061531.56322-1-ming.li@zohomail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 1c6b4cea | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Add cxl_test accelerator driver
Add a type2 accelerator mock driver for the platform device that simulates a CXL type2 device. The driver exercises the same minimal API calls that a real C
cxl/test: Add cxl_test accelerator driver
Add a type2 accelerator mock driver for the platform device that simulates a CXL type2 device. The driver exercises the same minimal API calls that a real CXL type2 driver would utilize.
Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-8-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| b3df5a5a | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Fixup hdm init for auto region to support type2
Add support to setup initialization of decoders in order to support type2 auto region.
Reviewed-by: Alison Schofield <alison.schofield@inte
cxl/test: Fixup hdm init for auto region to support type2
Add support to setup initialization of decoders in order to support type2 auto region.
Reviewed-by: Alison Schofield <alison.schofield@intel.com> Tested-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-7-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 98ba41c3 | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Propagate -ENOMEM on platform_device_alloc() failures
Set rc = -ENOMEM at every platform_device_alloc() failure site in cxl_rch_topo_init(), cxl_single_topo_init() and cxl_test_init() so t
cxl/test: Propagate -ENOMEM on platform_device_alloc() failures
Set rc = -ENOMEM at every platform_device_alloc() failure site in cxl_rch_topo_init(), cxl_single_topo_init() and cxl_test_init() so the failure is propagated and the module load aborts cleanly.
The cxl_acpi allocation site originates in the commit below, while the host-bridge/root-port/uport/dport allocation sites fixed here were added later in the single-host and RCH topology configs.
Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy") Fixes: e41c8452b9b2 ("tools/testing/cxl: Add a single-port host-bridge regression config") Fixes: c9435dbee119 ("tools/testing/cxl: Add an RCH topology") Assisted-by: Claude:claude-opus-4-8 Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-6-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 6b2e5851 | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Add hierarchy enumeration support for type2 device
Add enumeration of type2 device hierarchy in cxl-test. The type2 device is setup to be directly attached to a root port instead of rp ->
cxl/test: Add hierarchy enumeration support for type2 device
Add enumeration of type2 device hierarchy in cxl-test. The type2 device is setup to be directly attached to a root port instead of rp -> switch -> device that type3 hierarchy is setup..
Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-5-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| a6d37152 | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Refactor platform device enumerations
Split all the host bridges, rootports, upstream and downstream ports enumerations to separate helper functions. This should make adding type2 hierarch
cxl/test: Refactor platform device enumerations
Split all the host bridges, rootports, upstream and downstream ports enumerations to separate helper functions. This should make adding type2 hierarchy easier later on.
Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| fc8fc576 | 30-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Add type2 support for mock CFMWS0
Add a module parameter 'type2_test' for triggering type2 test support in cxl_test. Setup the CFMWS0 configuration to be type2 when 'type2_test' is set.
T
cxl/test: Add type2 support for mock CFMWS0
Add a module parameter 'type2_test' for triggering type2 test support in cxl_test. Setup the CFMWS0 configuration to be type2 when 'type2_test' is set.
Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260629221104.3891733-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 769f0b35 | 12-Jun-2026 |
Richard Cheng <icheng@nvidia.com> |
tools/testing/cxl: Resolve auto-region decoder targets like real HW
The mock auto-region created at module load wrote switch and host-bridge decoder target[] directly, in addition to target_map[]. R
tools/testing/cxl: Resolve auto-region decoder targets like real HW
The mock auto-region created at module load wrote switch and host-bridge decoder target[] directly, in addition to target_map[]. Real HW programs only target_map[] and resolves target[] as dports enumerate, via update_decoder_targets(). Region replay already follows that ordering, the initial auto-region did not.
Drop the direct target[] writes and call cxl_port_update_decoder_targets() so target[] is resolved the same way as real HW and region replay, exercising more of the auto-region driver path.
This is inspired by the discussion [1] below:
[1]: https://lore.kernel.org/all/20260521084806.28232-1-icheng@nvidia.com/
Suggested-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Richard Cheng <icheng@nvidia.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com?> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20260612011227.4220-1-icheng@nvidia.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| dfe28c85 | 12-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Add check after kzalloc() memory in alloc_mock_res()
alloc_mock_res() calls kzalloc() without checking the return value. Add scope based resource management to deal with the allocated memo
cxl/test: Add check after kzalloc() memory in alloc_mock_res()
alloc_mock_res() calls kzalloc() without checking the return value. Add scope based resource management to deal with the allocated memory cleanly.
Reported-by: sashiko-bot Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy") Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260611230305.197390-1-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 50cc34be | 12-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Unregister cxl_acpi in cxl_test_init() error path
In cxl_test_init(), Once cxl_mock_platform_device_add() succeeds, all error paths after needs to call platform_device_unregister() instead
cxl/test: Unregister cxl_acpi in cxl_test_init() error path
In cxl_test_init(), Once cxl_mock_platform_device_add() succeeds, all error paths after needs to call platform_device_unregister() instead of platform_device_put() to clean up.
Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy") Reported-by: sashiko-bot Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260611230355.198912-1-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 60f065db | 05-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Zero out LSA backing memory to avoid leaking to user
Memory through vmalloc() is not zeroed out. When this memory is copied into output payload, it leaks memory content to user. Use vzallo
cxl/test: Zero out LSA backing memory to avoid leaking to user
Memory through vmalloc() is not zeroed out. When this memory is copied into output payload, it leaks memory content to user. Use vzalloc() instead to zero out the memory.
Suggested-by: sashiko-bot Link: https://lore.kernel.org/linux-cxl/20260605173146.2B9A31F00893@smtp.kernel.org/ Fixes: 7d3eb23c4ccf ("tools/testing/cxl: Introduce a mock memory device + driver") Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260605184426.4070913-1-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 81eafcad | 05-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Fix integer overflow in mock LSA bounds checks
Pre-existing issue discovered by sashiko-bot.
mock_get_lsa() and mock_set_lsa() validate the requested LSA range with "offset + length > LSA
cxl/test: Fix integer overflow in mock LSA bounds checks
Pre-existing issue discovered by sashiko-bot.
mock_get_lsa() and mock_set_lsa() validate the requested LSA range with "offset + length > LSA_SIZE". Both offset and length are u32 and, in mock_get_lsa(), both are taken directly from the user-supplied payload. The addition is evaluated modulo 2^32, so a large offset combined with a small length wraps around and passes the check.
Rewrite the checks to first bound offset, then compare length against the remaining LSA size.
Suggested-by: sashiko-bot Fixes: 7d3eb23c4ccf ("tools/testing/cxl: Introduce a mock memory device + driver") Link: https://lore.kernel.org/linux-cxl/20260605143748.235271F00893@smtp.kernel.org/ Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 71a1def1 | 05-Jun-2026 |
Dave Jiang <dave.jiang@intel.com> |
cxl/test: Verify cmd->size_in before accessing payload
Several mock mailbox handlers access input payload fields before verifying that cmd->size_in is large enough for the corresponding structure.
cxl/test: Verify cmd->size_in before accessing payload
Several mock mailbox handlers access input payload fields before verifying that cmd->size_in is large enough for the corresponding structure.
To ensure invalid commands are rejected before any payload data is consumed, add missing size checks and move existing checks ahead of the first payload field access.
[dj: Updated commit log per Alison's comments. ]
Fixes: 7d3eb23c4ccf ("tools/testing/cxl: Introduce a mock memory device + driver") Fixes: d1dca858f058 ("cxl/test: Add generic mock events") Fixes: f6448cb5f2f3 ("tools/testing/cxl: add firmware update emulation to CXL memdevs") Fixes: e77e9c107978 ("cxl/test: Add Get Feature support to cxl_test") Link: https://lore.kernel.org/linux-cxl/20260605143748.235271F00893@smtp.kernel.org/ Suggested-by: sashiko-bot Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 08326b92 | 20-May-2026 |
Dan Williams <djbw@kernel.org> |
cxl/test: Fix __fortify_panic
Fix a runtime assertion in setup_xor_mapping(). Fortify complains that it is potentially overflowing the xormaps array per __counted_by(nr_maps). Quiet the false positi
cxl/test: Fix __fortify_panic
Fix a runtime assertion in setup_xor_mapping(). Fortify complains that it is potentially overflowing the xormaps array per __counted_by(nr_maps). Quiet the false positive by initializing @nr_maps earlier.
memcpy: detected buffer overflow: 32 byte write of buffer size 0 WARNING: lib/string_helpers.c:1036 at __fortify_report+0x4d/0xa0, CPU#8: modprobe/2728 Call Trace: __fortify_panic+0xd/0xf setup_xor_mapping+0x6c/0xa0 [cxl_translate]
[ dj: Fixed up @nr_entries to @nr_maps in commit log. ]
Fixes: 06377c54a133 ("cxl/test: Add cxl_translate module for address translation testing") Signed-off-by: Dan Williams <djbw@kernel.org> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20260519221204.1517773-3-djbw@kernel.org Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 303d3284 | 03-Apr-2026 |
Dave Jiang <dave.jiang@intel.com> |
Merge branch 'for-7.1/dax-hmem' into cxl-for-next
The series addresses conflicts between HMEM and CXL when handling Soft Reserved memory ranges. CXL will try best effort in claiming the Soft Reserve
Merge branch 'for-7.1/dax-hmem' into cxl-for-next
The series addresses conflicts between HMEM and CXL when handling Soft Reserved memory ranges. CXL will try best effort in claiming the Soft Reserved memory region that are CXL regions. If fails, it will punt back to HMEM.
tools/testing/cxl: Test dax_hmem takeover of CXL regions tools/testing/cxl: Simulate auto-assembly failure dax/hmem: Parent dax_hmem devices dax/hmem: Fix singleton confusion between dax_hmem_work and hmem devices dax/hmem: Reduce visibility of dax_cxl coordination symbols cxl/region: Constify cxl_region_resource_contains() cxl/region: Limit visibility of cxl_region_contains_resource() dax/cxl: Fix HMEM dependencies cxl/region: Fix use-after-free from auto assembly failure dax/hmem, cxl: Defer and resolve Soft Reserved ownership cxl/region: Add helper to check Soft Reserved containment by CXL regions dax: Track all dax_region allocations under a global resource tree dax/cxl, hmem: Initialize hmem early and defer dax_cxl binding dax/hmem: Gate Soft Reserved deferral on DEV_DAX_CXL dax/hmem: Request cxl_acpi and cxl_pci before walking Soft Reserved ranges dax/hmem: Factor HMEM registration into __hmem_register_device() dax/bus: Use dax_region_put() in alloc_dax_region() error path
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