| a6961e2c | 06-Nov-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms
Similarly to stm32mp23x/25x platforms, the RIFSC is a firewall controller. Declare it as an access controller, keep the "sim
arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms
Similarly to stm32mp23x/25x platforms, the RIFSC is a firewall controller. Declare it as an access controller, keep the "simple-bus" compatible in case CONFIG_STM32_FIREWALL is not set and update the child nodes.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251106-rifsc_debugfs-v2-2-f90e94ae756d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| e613ef5c | 23-Oct-2025 |
Antonio Borneo <antonio.borneo@foss.st.com> |
arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
On board stm32mp257f-ev1, the propagation delay between eth1/eth2 and the external PHY requires a compensation to guarantee that
arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
On board stm32mp257f-ev1, the propagation delay between eth1/eth2 and the external PHY requires a compensation to guarantee that no packet get lost in all the working conditions.
Add I/O synchronization properties in pinctrl on all the RGMII data pins, activating re-sampling on both edges of the clock.
Co-developed-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20251023132700.1199871-13-antonio.borneo@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 53c18dc0 | 10-Sep-2025 |
Amelie Delaunay <amelie.delaunay@foss.st.com> |
arm64: dts: st: fix memory region size on stm32mp235f-dk
STM32MP23x SoCs provide a DDR controller supporting up to 4GB/16-bit. The control pin to properly configure 4GB/16-bit is not routed on stm32
arm64: dts: st: fix memory region size on stm32mp235f-dk
STM32MP23x SoCs provide a DDR controller supporting up to 4GB/16-bit. The control pin to properly configure 4GB/16-bit is not routed on stm32mp235f-dk, that's why the board only supports 2GB.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-2-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 7bfa81d4 | 10-Sep-2025 |
Amelie Delaunay <amelie.delaunay@foss.st.com> |
arm64: dts: st: remove gpioj and gpiok banks from stm32mp231
STM32MP23x supports AJ, AK and AL packages, where PI12 to PI15, PJ0 to PJ15 (whole J bank) and PK0 to PK7 (whole K bank) pins are not ava
arm64: dts: st: remove gpioj and gpiok banks from stm32mp231
STM32MP23x supports AJ, AK and AL packages, where PI12 to PI15, PJ0 to PJ15 (whole J bank) and PK0 to PK7 (whole K bank) pins are not available.
It means gpioj and gpiok nodes are useless in stm32mp231. Remove them.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-1-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| df4eb8bb | 04-Sep-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board.
Sig
arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-4-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 58f29beb | 04-Sep-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controll
arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controller or be connected to the internal TSN capable switch. For this board, keep the standalone setup. Also enable this peripheral on the stm32mp257f-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-3-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 74e42b3c | 04-Sep-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board.
Sig
arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-2-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 86803282 | 22-Aug-2025 |
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> |
arm64: dts: st: enable display support on stm32mp257f-ev1 board
Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel L
arm64: dts: st: enable display support on stm32mp257f-ev1 board
Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-13-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 092f7634 | 22-Aug-2025 |
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> |
arm64: dts: st: add clock-cells to syscfg node on stm32mp251
Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree.
Signed-off-by: Raphael Gallais-Pou
arm64: dts: st: add clock-cells to syscfg node on stm32mp251
Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-12-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| c067119b | 22-Aug-2025 |
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> |
arm64: dts: st: add lvds support on stm32mp255
The LVDS is used on STM32MP2 as a display interface.
Add the LVDS node.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by
arm64: dts: st: add lvds support on stm32mp255
The LVDS is used on STM32MP2 as a display interface.
Add the LVDS node.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 84b78bc2 | 22-Aug-2025 |
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> |
arm64: dts: st: add ltdc support on stm32mp255
Add the LTDC node for stm32mp255 SoC and handle its loopback clocks.
ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantic
arm64: dts: st: add ltdc support on stm32mp255
Add the LTDC node for stm32mp255 SoC and handle its loopback clocks.
ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-10-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 114e282d | 22-Aug-2025 |
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> |
arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display
arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces.
Add the LTDC node.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-9-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 30793e01 | 20-Aug-2025 |
Christian Bruel <christian.bruel@foss.st.com> |
arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode.
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link:
arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode.
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250820075411.1178729-12-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 73d536ae | 20-Aug-2025 |
Christian Bruel <christian.bruel@foss.st.com> |
arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode
Signed-off-by: Christian Bruel
arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-11-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 0ecdf6d2 | 20-Aug-2025 |
Christian Bruel <christian.bruel@foss.st.com> |
arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode
Supports Gen1/Gen2, sin
arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode
Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| f398bb61 | 11-Jul-2025 |
Clément Le Goffic <clement.legoffic@foss.st.com> |
arm64: dts: st: add Hardware debug port (HDP) on stm32mp25
Add the hdp devicetree node for stm32mp25 SoC family
Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to outpu
arm64: dts: st: add Hardware debug port (HDP) on stm32mp25
Add the hdp devicetree node for stm32mp25 SoC family
Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 1a32f742 | 15-May-2025 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm64: dts: st: remove empty line in stm32mp251.dtsi
Remove unnecessary empty line in stm32mp251.dtsi
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/
arm64: dts: st: remove empty line in stm32mp251.dtsi
Remove unnecessary empty line in stm32mp251.dtsi
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250515151238.2.Ia426b4ef1d1200247a950ef9abd54a94dc520acb@changeid Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 986fa072 | 10-Jan-2025 |
Fabrice Gasnier <fabrice.gasnier@foss.st.com> |
arm64: dts: st: add timer nodes on stm32mp257f-ev1
Configure timer nodes on stm32mp257f-ev1: - Timer3 CH2 is available on mikroBUS connector for PWM - timer8 CH1, timer8 CH4, timer10 CH1 and timer12
arm64: dts: st: add timer nodes on stm32mp257f-ev1
Configure timer nodes on stm32mp257f-ev1: - Timer3 CH2 is available on mikroBUS connector for PWM - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector. Timers are kept disabled by default, so the pins can be used for any other purpose (and the timers can be assigned to any of the processors). Arbitrary choice is to use all these timers as PWM (or counter on internal clock signal), except for timer10 that is configured with CH1 as an input (for capture).
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-9-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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| 0b22e2e5 | 10-Jan-2025 |
Fabrice Gasnier <fabrice.gasnier@foss.st.com> |
arm64: dts: st: add timer pins for stm32mp257f-ev1
Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10
arm64: dts: st: add timer pins for stm32mp257f-ev1
Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector Arbitrary define all these pins to be used as PWM (output) channels, except for timer10 CH1, to be used as counter input.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-8-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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