xref: /linux/drivers/gpu/drm/i915/display/skl_universal_plane.c (revision 113ff0e048ff11e4c52ae97f9fa59fd39c1c0f6a)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include <drm/drm_atomic_helper.h>
7 #include <drm/drm_blend.h>
8 #include <drm/drm_damage_helper.h>
9 #include <drm/drm_fourcc.h>
10 
11 #include "i915_drv.h"
12 #include "i915_reg.h"
13 #include "intel_atomic_plane.h"
14 #include "intel_bo.h"
15 #include "intel_de.h"
16 #include "intel_display_irq.h"
17 #include "intel_display_types.h"
18 #include "intel_dpt.h"
19 #include "intel_fb.h"
20 #include "intel_fbc.h"
21 #include "intel_frontbuffer.h"
22 #include "intel_psr.h"
23 #include "intel_psr_regs.h"
24 #include "skl_scaler.h"
25 #include "skl_universal_plane.h"
26 #include "skl_universal_plane_regs.h"
27 #include "skl_watermark.h"
28 #include "pxp/intel_pxp.h"
29 
30 static const u32 skl_plane_formats[] = {
31 	DRM_FORMAT_C8,
32 	DRM_FORMAT_RGB565,
33 	DRM_FORMAT_XRGB8888,
34 	DRM_FORMAT_XBGR8888,
35 	DRM_FORMAT_ARGB8888,
36 	DRM_FORMAT_ABGR8888,
37 	DRM_FORMAT_XRGB2101010,
38 	DRM_FORMAT_XBGR2101010,
39 	DRM_FORMAT_XRGB16161616F,
40 	DRM_FORMAT_XBGR16161616F,
41 	DRM_FORMAT_YUYV,
42 	DRM_FORMAT_YVYU,
43 	DRM_FORMAT_UYVY,
44 	DRM_FORMAT_VYUY,
45 	DRM_FORMAT_XYUV8888,
46 };
47 
48 static const u32 skl_planar_formats[] = {
49 	DRM_FORMAT_C8,
50 	DRM_FORMAT_RGB565,
51 	DRM_FORMAT_XRGB8888,
52 	DRM_FORMAT_XBGR8888,
53 	DRM_FORMAT_ARGB8888,
54 	DRM_FORMAT_ABGR8888,
55 	DRM_FORMAT_XRGB2101010,
56 	DRM_FORMAT_XBGR2101010,
57 	DRM_FORMAT_XRGB16161616F,
58 	DRM_FORMAT_XBGR16161616F,
59 	DRM_FORMAT_YUYV,
60 	DRM_FORMAT_YVYU,
61 	DRM_FORMAT_UYVY,
62 	DRM_FORMAT_VYUY,
63 	DRM_FORMAT_NV12,
64 	DRM_FORMAT_XYUV8888,
65 };
66 
67 static const u32 glk_planar_formats[] = {
68 	DRM_FORMAT_C8,
69 	DRM_FORMAT_RGB565,
70 	DRM_FORMAT_XRGB8888,
71 	DRM_FORMAT_XBGR8888,
72 	DRM_FORMAT_ARGB8888,
73 	DRM_FORMAT_ABGR8888,
74 	DRM_FORMAT_XRGB2101010,
75 	DRM_FORMAT_XBGR2101010,
76 	DRM_FORMAT_XRGB16161616F,
77 	DRM_FORMAT_XBGR16161616F,
78 	DRM_FORMAT_YUYV,
79 	DRM_FORMAT_YVYU,
80 	DRM_FORMAT_UYVY,
81 	DRM_FORMAT_VYUY,
82 	DRM_FORMAT_NV12,
83 	DRM_FORMAT_XYUV8888,
84 	DRM_FORMAT_P010,
85 	DRM_FORMAT_P012,
86 	DRM_FORMAT_P016,
87 };
88 
89 static const u32 icl_sdr_y_plane_formats[] = {
90 	DRM_FORMAT_C8,
91 	DRM_FORMAT_RGB565,
92 	DRM_FORMAT_XRGB8888,
93 	DRM_FORMAT_XBGR8888,
94 	DRM_FORMAT_ARGB8888,
95 	DRM_FORMAT_ABGR8888,
96 	DRM_FORMAT_XRGB2101010,
97 	DRM_FORMAT_XBGR2101010,
98 	DRM_FORMAT_ARGB2101010,
99 	DRM_FORMAT_ABGR2101010,
100 	DRM_FORMAT_YUYV,
101 	DRM_FORMAT_YVYU,
102 	DRM_FORMAT_UYVY,
103 	DRM_FORMAT_VYUY,
104 	DRM_FORMAT_Y210,
105 	DRM_FORMAT_Y212,
106 	DRM_FORMAT_Y216,
107 	DRM_FORMAT_XYUV8888,
108 	DRM_FORMAT_XVYU2101010,
109 	DRM_FORMAT_XVYU12_16161616,
110 	DRM_FORMAT_XVYU16161616,
111 };
112 
113 static const u32 icl_sdr_uv_plane_formats[] = {
114 	DRM_FORMAT_C8,
115 	DRM_FORMAT_RGB565,
116 	DRM_FORMAT_XRGB8888,
117 	DRM_FORMAT_XBGR8888,
118 	DRM_FORMAT_ARGB8888,
119 	DRM_FORMAT_ABGR8888,
120 	DRM_FORMAT_XRGB2101010,
121 	DRM_FORMAT_XBGR2101010,
122 	DRM_FORMAT_ARGB2101010,
123 	DRM_FORMAT_ABGR2101010,
124 	DRM_FORMAT_YUYV,
125 	DRM_FORMAT_YVYU,
126 	DRM_FORMAT_UYVY,
127 	DRM_FORMAT_VYUY,
128 	DRM_FORMAT_NV12,
129 	DRM_FORMAT_P010,
130 	DRM_FORMAT_P012,
131 	DRM_FORMAT_P016,
132 	DRM_FORMAT_Y210,
133 	DRM_FORMAT_Y212,
134 	DRM_FORMAT_Y216,
135 	DRM_FORMAT_XYUV8888,
136 	DRM_FORMAT_XVYU2101010,
137 	DRM_FORMAT_XVYU12_16161616,
138 	DRM_FORMAT_XVYU16161616,
139 };
140 
141 static const u32 icl_hdr_plane_formats[] = {
142 	DRM_FORMAT_C8,
143 	DRM_FORMAT_RGB565,
144 	DRM_FORMAT_XRGB8888,
145 	DRM_FORMAT_XBGR8888,
146 	DRM_FORMAT_ARGB8888,
147 	DRM_FORMAT_ABGR8888,
148 	DRM_FORMAT_XRGB2101010,
149 	DRM_FORMAT_XBGR2101010,
150 	DRM_FORMAT_ARGB2101010,
151 	DRM_FORMAT_ABGR2101010,
152 	DRM_FORMAT_XRGB16161616F,
153 	DRM_FORMAT_XBGR16161616F,
154 	DRM_FORMAT_ARGB16161616F,
155 	DRM_FORMAT_ABGR16161616F,
156 	DRM_FORMAT_YUYV,
157 	DRM_FORMAT_YVYU,
158 	DRM_FORMAT_UYVY,
159 	DRM_FORMAT_VYUY,
160 	DRM_FORMAT_NV12,
161 	DRM_FORMAT_P010,
162 	DRM_FORMAT_P012,
163 	DRM_FORMAT_P016,
164 	DRM_FORMAT_Y210,
165 	DRM_FORMAT_Y212,
166 	DRM_FORMAT_Y216,
167 	DRM_FORMAT_XYUV8888,
168 	DRM_FORMAT_XVYU2101010,
169 	DRM_FORMAT_XVYU12_16161616,
170 	DRM_FORMAT_XVYU16161616,
171 };
172 
173 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
174 {
175 	switch (format) {
176 	case PLANE_CTL_FORMAT_RGB_565:
177 		return DRM_FORMAT_RGB565;
178 	case PLANE_CTL_FORMAT_NV12:
179 		return DRM_FORMAT_NV12;
180 	case PLANE_CTL_FORMAT_XYUV:
181 		return DRM_FORMAT_XYUV8888;
182 	case PLANE_CTL_FORMAT_P010:
183 		return DRM_FORMAT_P010;
184 	case PLANE_CTL_FORMAT_P012:
185 		return DRM_FORMAT_P012;
186 	case PLANE_CTL_FORMAT_P016:
187 		return DRM_FORMAT_P016;
188 	case PLANE_CTL_FORMAT_Y210:
189 		return DRM_FORMAT_Y210;
190 	case PLANE_CTL_FORMAT_Y212:
191 		return DRM_FORMAT_Y212;
192 	case PLANE_CTL_FORMAT_Y216:
193 		return DRM_FORMAT_Y216;
194 	case PLANE_CTL_FORMAT_Y410:
195 		return DRM_FORMAT_XVYU2101010;
196 	case PLANE_CTL_FORMAT_Y412:
197 		return DRM_FORMAT_XVYU12_16161616;
198 	case PLANE_CTL_FORMAT_Y416:
199 		return DRM_FORMAT_XVYU16161616;
200 	default:
201 	case PLANE_CTL_FORMAT_XRGB_8888:
202 		if (rgb_order) {
203 			if (alpha)
204 				return DRM_FORMAT_ABGR8888;
205 			else
206 				return DRM_FORMAT_XBGR8888;
207 		} else {
208 			if (alpha)
209 				return DRM_FORMAT_ARGB8888;
210 			else
211 				return DRM_FORMAT_XRGB8888;
212 		}
213 	case PLANE_CTL_FORMAT_XRGB_2101010:
214 		if (rgb_order) {
215 			if (alpha)
216 				return DRM_FORMAT_ABGR2101010;
217 			else
218 				return DRM_FORMAT_XBGR2101010;
219 		} else {
220 			if (alpha)
221 				return DRM_FORMAT_ARGB2101010;
222 			else
223 				return DRM_FORMAT_XRGB2101010;
224 		}
225 	case PLANE_CTL_FORMAT_XRGB_16161616F:
226 		if (rgb_order) {
227 			if (alpha)
228 				return DRM_FORMAT_ABGR16161616F;
229 			else
230 				return DRM_FORMAT_XBGR16161616F;
231 		} else {
232 			if (alpha)
233 				return DRM_FORMAT_ARGB16161616F;
234 			else
235 				return DRM_FORMAT_XRGB16161616F;
236 		}
237 	}
238 }
239 
240 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
241 {
242 	struct intel_display *display = &i915->display;
243 
244 	if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))
245 		return BIT(PLANE_4) | BIT(PLANE_5);
246 	else
247 		return BIT(PLANE_6) | BIT(PLANE_7);
248 }
249 
250 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
251 			 enum plane_id plane_id)
252 {
253 	return DISPLAY_VER(dev_priv) >= 11 &&
254 		icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
255 }
256 
257 u8 icl_hdr_plane_mask(void)
258 {
259 	return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
260 }
261 
262 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
263 {
264 	return DISPLAY_VER(dev_priv) >= 11 &&
265 		icl_hdr_plane_mask() & BIT(plane_id);
266 }
267 
268 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
269 			       const struct intel_plane_state *plane_state)
270 {
271 	unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
272 
273 	/* two pixels per clock */
274 	return DIV_ROUND_UP(pixel_rate, 2);
275 }
276 
277 static void
278 glk_plane_ratio(const struct intel_plane_state *plane_state,
279 		unsigned int *num, unsigned int *den)
280 {
281 	const struct drm_framebuffer *fb = plane_state->hw.fb;
282 
283 	if (fb->format->cpp[0] == 8) {
284 		*num = 10;
285 		*den = 8;
286 	} else {
287 		*num = 1;
288 		*den = 1;
289 	}
290 }
291 
292 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
293 			       const struct intel_plane_state *plane_state)
294 {
295 	unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
296 	unsigned int num, den;
297 
298 	glk_plane_ratio(plane_state, &num, &den);
299 
300 	/* two pixels per clock */
301 	return DIV_ROUND_UP(pixel_rate * num, 2 * den);
302 }
303 
304 static void
305 skl_plane_ratio(const struct intel_plane_state *plane_state,
306 		unsigned int *num, unsigned int *den)
307 {
308 	const struct drm_framebuffer *fb = plane_state->hw.fb;
309 
310 	if (fb->format->cpp[0] == 8) {
311 		*num = 9;
312 		*den = 8;
313 	} else {
314 		*num = 1;
315 		*den = 1;
316 	}
317 }
318 
319 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
320 			       const struct intel_plane_state *plane_state)
321 {
322 	unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
323 	unsigned int num, den;
324 
325 	skl_plane_ratio(plane_state, &num, &den);
326 
327 	return DIV_ROUND_UP(pixel_rate * num, den);
328 }
329 
330 static int skl_plane_max_width(const struct drm_framebuffer *fb,
331 			       int color_plane,
332 			       unsigned int rotation)
333 {
334 	int cpp = fb->format->cpp[color_plane];
335 
336 	switch (fb->modifier) {
337 	case DRM_FORMAT_MOD_LINEAR:
338 	case I915_FORMAT_MOD_X_TILED:
339 		/*
340 		 * Validated limit is 4k, but has 5k should
341 		 * work apart from the following features:
342 		 * - Ytile (already limited to 4k)
343 		 * - FP16 (already limited to 4k)
344 		 * - render compression (already limited to 4k)
345 		 * - KVMR sprite and cursor (don't care)
346 		 * - horizontal panning (TODO verify this)
347 		 * - pipe and plane scaling (TODO verify this)
348 		 */
349 		if (cpp == 8)
350 			return 4096;
351 		else
352 			return 5120;
353 	case I915_FORMAT_MOD_Y_TILED_CCS:
354 	case I915_FORMAT_MOD_Yf_TILED_CCS:
355 		/* FIXME AUX plane? */
356 	case I915_FORMAT_MOD_Y_TILED:
357 	case I915_FORMAT_MOD_Yf_TILED:
358 		if (cpp == 8)
359 			return 2048;
360 		else
361 			return 4096;
362 	default:
363 		MISSING_CASE(fb->modifier);
364 		return 2048;
365 	}
366 }
367 
368 static int glk_plane_max_width(const struct drm_framebuffer *fb,
369 			       int color_plane,
370 			       unsigned int rotation)
371 {
372 	int cpp = fb->format->cpp[color_plane];
373 
374 	switch (fb->modifier) {
375 	case DRM_FORMAT_MOD_LINEAR:
376 	case I915_FORMAT_MOD_X_TILED:
377 		if (cpp == 8)
378 			return 4096;
379 		else
380 			return 5120;
381 	case I915_FORMAT_MOD_Y_TILED_CCS:
382 	case I915_FORMAT_MOD_Yf_TILED_CCS:
383 		/* FIXME AUX plane? */
384 	case I915_FORMAT_MOD_Y_TILED:
385 	case I915_FORMAT_MOD_Yf_TILED:
386 		if (cpp == 8)
387 			return 2048;
388 		else
389 			return 5120;
390 	default:
391 		MISSING_CASE(fb->modifier);
392 		return 2048;
393 	}
394 }
395 
396 static int icl_plane_min_width(const struct drm_framebuffer *fb,
397 			       int color_plane,
398 			       unsigned int rotation)
399 {
400 	/* Wa_14011264657, Wa_14011050563: gen11+ */
401 	switch (fb->format->format) {
402 	case DRM_FORMAT_C8:
403 		return 18;
404 	case DRM_FORMAT_RGB565:
405 		return 10;
406 	case DRM_FORMAT_XRGB8888:
407 	case DRM_FORMAT_XBGR8888:
408 	case DRM_FORMAT_ARGB8888:
409 	case DRM_FORMAT_ABGR8888:
410 	case DRM_FORMAT_XRGB2101010:
411 	case DRM_FORMAT_XBGR2101010:
412 	case DRM_FORMAT_ARGB2101010:
413 	case DRM_FORMAT_ABGR2101010:
414 	case DRM_FORMAT_XVYU2101010:
415 	case DRM_FORMAT_Y212:
416 	case DRM_FORMAT_Y216:
417 		return 6;
418 	case DRM_FORMAT_NV12:
419 		return 20;
420 	case DRM_FORMAT_P010:
421 	case DRM_FORMAT_P012:
422 	case DRM_FORMAT_P016:
423 		return 12;
424 	case DRM_FORMAT_XRGB16161616F:
425 	case DRM_FORMAT_XBGR16161616F:
426 	case DRM_FORMAT_ARGB16161616F:
427 	case DRM_FORMAT_ABGR16161616F:
428 	case DRM_FORMAT_XVYU12_16161616:
429 	case DRM_FORMAT_XVYU16161616:
430 		return 4;
431 	default:
432 		return 1;
433 	}
434 }
435 
436 static int xe3_plane_max_width(const struct drm_framebuffer *fb,
437 			       int color_plane,
438 			       unsigned int rotation)
439 {
440 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
441 		return 4096;
442 	else
443 		return 6144;
444 }
445 
446 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
447 				   int color_plane,
448 				   unsigned int rotation)
449 {
450 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
451 		return 4096;
452 	else
453 		return 5120;
454 }
455 
456 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
457 				   int color_plane,
458 				   unsigned int rotation)
459 {
460 	return 5120;
461 }
462 
463 static int skl_plane_max_height(const struct drm_framebuffer *fb,
464 				int color_plane,
465 				unsigned int rotation)
466 {
467 	return 4096;
468 }
469 
470 static int icl_plane_max_height(const struct drm_framebuffer *fb,
471 				int color_plane,
472 				unsigned int rotation)
473 {
474 	return 4320;
475 }
476 
477 static unsigned int
478 plane_max_stride(struct intel_plane *plane,
479 		 u32 pixel_format, u64 modifier,
480 		 unsigned int rotation,
481 		 unsigned int max_pixels,
482 		 unsigned int max_bytes)
483 {
484 	const struct drm_format_info *info = drm_format_info(pixel_format);
485 	int cpp = info->cpp[0];
486 
487 	if (drm_rotation_90_or_270(rotation))
488 		return min(max_pixels, max_bytes / cpp);
489 	else
490 		return min(max_pixels * cpp, max_bytes);
491 }
492 
493 static unsigned int
494 adl_plane_max_stride(struct intel_plane *plane,
495 		     u32 pixel_format, u64 modifier,
496 		     unsigned int rotation)
497 {
498 	unsigned int max_pixels = 65536; /* PLANE_OFFSET limit */
499 	unsigned int max_bytes = 128 * 1024;
500 
501 	return plane_max_stride(plane, pixel_format,
502 				modifier, rotation,
503 				max_pixels, max_bytes);
504 }
505 
506 static unsigned int
507 skl_plane_max_stride(struct intel_plane *plane,
508 		     u32 pixel_format, u64 modifier,
509 		     unsigned int rotation)
510 {
511 	unsigned int max_pixels = 8192; /* PLANE_OFFSET limit */
512 	unsigned int max_bytes = 32 * 1024;
513 
514 	return plane_max_stride(plane, pixel_format,
515 				modifier, rotation,
516 				max_pixels, max_bytes);
517 }
518 
519 static u32 tgl_plane_min_alignment(struct intel_plane *plane,
520 				   const struct drm_framebuffer *fb,
521 				   int color_plane)
522 {
523 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
524 	/* PLANE_SURF GGTT -> DPT alignment */
525 	int mult = intel_fb_uses_dpt(fb) ? 512 : 1;
526 
527 	/* AUX_DIST needs only 4K alignment */
528 	if (intel_fb_is_ccs_aux_plane(fb, color_plane))
529 		return mult * 4 * 1024;
530 
531 	switch (fb->modifier) {
532 	case DRM_FORMAT_MOD_LINEAR:
533 	case I915_FORMAT_MOD_X_TILED:
534 	case I915_FORMAT_MOD_Y_TILED:
535 	case I915_FORMAT_MOD_4_TILED:
536 		/*
537 		 * FIXME ADL sees GGTT/DMAR faults with async
538 		 * flips unless we align to 16k at least.
539 		 * Figure out what's going on here...
540 		 */
541 		if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915))
542 			return mult * 16 * 1024;
543 		return mult * 4 * 1024;
544 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
545 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
546 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
547 	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
548 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
549 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
550 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
551 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
552 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
553 	case I915_FORMAT_MOD_4_TILED_BMG_CCS:
554 	case I915_FORMAT_MOD_4_TILED_LNL_CCS:
555 		/*
556 		 * Align to at least 4x1 main surface
557 		 * tiles (16K) to match 64B of AUX.
558 		 */
559 		return max(mult * 4 * 1024, 16 * 1024);
560 	default:
561 		MISSING_CASE(fb->modifier);
562 		return 0;
563 	}
564 }
565 
566 static u32 skl_plane_min_alignment(struct intel_plane *plane,
567 				   const struct drm_framebuffer *fb,
568 				   int color_plane)
569 {
570 	/*
571 	 * AUX_DIST needs only 4K alignment,
572 	 * as does ICL UV PLANE_SURF.
573 	 */
574 	if (color_plane != 0)
575 		return 4 * 1024;
576 
577 	switch (fb->modifier) {
578 	case DRM_FORMAT_MOD_LINEAR:
579 	case I915_FORMAT_MOD_X_TILED:
580 		return 256 * 1024;
581 	case I915_FORMAT_MOD_Y_TILED_CCS:
582 	case I915_FORMAT_MOD_Yf_TILED_CCS:
583 	case I915_FORMAT_MOD_Y_TILED:
584 	case I915_FORMAT_MOD_Yf_TILED:
585 		return 1 * 1024 * 1024;
586 	default:
587 		MISSING_CASE(fb->modifier);
588 		return 0;
589 	}
590 }
591 
592 /* Preoffset values for YUV to RGB Conversion */
593 #define PREOFF_YUV_TO_RGB_HI		0x1800
594 #define PREOFF_YUV_TO_RGB_ME		0x0000
595 #define PREOFF_YUV_TO_RGB_LO		0x1800
596 
597 #define  ROFF(x)          (((x) & 0xffff) << 16)
598 #define  GOFF(x)          (((x) & 0xffff) << 0)
599 #define  BOFF(x)          (((x) & 0xffff) << 16)
600 
601 /*
602  * Programs the input color space conversion stage for ICL HDR planes.
603  * Note that it is assumed that this stage always happens after YUV
604  * range correction. Thus, the input to this stage is assumed to be
605  * in full-range YCbCr.
606  */
607 static void
608 icl_program_input_csc(struct intel_dsb *dsb,
609 		      struct intel_plane *plane,
610 		      const struct intel_plane_state *plane_state)
611 {
612 	struct intel_display *display = to_intel_display(plane->base.dev);
613 	enum pipe pipe = plane->pipe;
614 	enum plane_id plane_id = plane->id;
615 
616 	static const u16 input_csc_matrix[][9] = {
617 		/*
618 		 * BT.601 full range YCbCr -> full range RGB
619 		 * The matrix required is :
620 		 * [1.000, 0.000, 1.371,
621 		 *  1.000, -0.336, -0.698,
622 		 *  1.000, 1.732, 0.0000]
623 		 */
624 		[DRM_COLOR_YCBCR_BT601] = {
625 			0x7AF8, 0x7800, 0x0,
626 			0x8B28, 0x7800, 0x9AC0,
627 			0x0, 0x7800, 0x7DD8,
628 		},
629 		/*
630 		 * BT.709 full range YCbCr -> full range RGB
631 		 * The matrix required is :
632 		 * [1.000, 0.000, 1.574,
633 		 *  1.000, -0.187, -0.468,
634 		 *  1.000, 1.855, 0.0000]
635 		 */
636 		[DRM_COLOR_YCBCR_BT709] = {
637 			0x7C98, 0x7800, 0x0,
638 			0x9EF8, 0x7800, 0xAC00,
639 			0x0, 0x7800,  0x7ED8,
640 		},
641 		/*
642 		 * BT.2020 full range YCbCr -> full range RGB
643 		 * The matrix required is :
644 		 * [1.000, 0.000, 1.474,
645 		 *  1.000, -0.1645, -0.5713,
646 		 *  1.000, 1.8814, 0.0000]
647 		 */
648 		[DRM_COLOR_YCBCR_BT2020] = {
649 			0x7BC8, 0x7800, 0x0,
650 			0x8928, 0x7800, 0xAA88,
651 			0x0, 0x7800, 0x7F10,
652 		},
653 	};
654 	const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
655 
656 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
657 			   ROFF(csc[0]) | GOFF(csc[1]));
658 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
659 			   BOFF(csc[2]));
660 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
661 			   ROFF(csc[3]) | GOFF(csc[4]));
662 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
663 			   BOFF(csc[5]));
664 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
665 			   ROFF(csc[6]) | GOFF(csc[7]));
666 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
667 			   BOFF(csc[8]));
668 
669 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
670 			   PREOFF_YUV_TO_RGB_HI);
671 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
672 			   PREOFF_YUV_TO_RGB_ME);
673 	intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
674 			   PREOFF_YUV_TO_RGB_LO);
675 	intel_de_write_dsb(display, dsb,
676 			   PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
677 	intel_de_write_dsb(display, dsb,
678 			   PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
679 	intel_de_write_dsb(display, dsb,
680 			   PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
681 }
682 
683 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
684 					  int color_plane, unsigned int rotation)
685 {
686 	/*
687 	 * The stride is either expressed as a multiple of 64 bytes chunks for
688 	 * linear buffers or in number of tiles for tiled buffers.
689 	 */
690 	if (is_surface_linear(fb, color_plane))
691 		return 64;
692 	else if (drm_rotation_90_or_270(rotation))
693 		return intel_tile_height(fb, color_plane);
694 	else
695 		return intel_tile_width_bytes(fb, color_plane);
696 }
697 
698 static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
699 			    int color_plane)
700 {
701 	const struct drm_framebuffer *fb = plane_state->hw.fb;
702 	unsigned int rotation = plane_state->hw.rotation;
703 	u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;
704 
705 	if (color_plane >= fb->format->num_planes)
706 		return 0;
707 
708 	return stride / skl_plane_stride_mult(fb, color_plane, rotation);
709 }
710 
711 static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
712 {
713 	if (!entry->end)
714 		return 0;
715 
716 	return PLANE_BUF_END(entry->end - 1) |
717 		PLANE_BUF_START(entry->start);
718 }
719 
720 static u32 xe3_plane_min_ddb_reg_val(const u16 *min_ddb,
721 				     const u16 *interim_ddb)
722 {
723 	u32 val = 0;
724 
725 	if (*min_ddb)
726 		val |= PLANE_MIN_DBUF_BLOCKS(*min_ddb);
727 
728 	if (*interim_ddb)
729 		val |= PLANE_INTERIM_DBUF_BLOCKS(*interim_ddb);
730 
731 	val |= val ? PLANE_AUTO_MIN_DBUF_EN : 0;
732 
733 	return val;
734 }
735 
736 static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
737 {
738 	u32 val = 0;
739 
740 	if (level->enable)
741 		val |= PLANE_WM_EN;
742 	if (level->ignore_lines)
743 		val |= PLANE_WM_IGNORE_LINES;
744 	if (level->auto_min_alloc_wm_enable)
745 		val |= PLANE_WM_AUTO_MIN_ALLOC_EN;
746 
747 	val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
748 	val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
749 
750 	return val;
751 }
752 
753 static void skl_write_plane_wm(struct intel_dsb *dsb,
754 			       struct intel_plane *plane,
755 			       const struct intel_crtc_state *crtc_state)
756 {
757 	struct intel_display *display = to_intel_display(plane->base.dev);
758 	enum plane_id plane_id = plane->id;
759 	enum pipe pipe = plane->pipe;
760 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
761 	const struct skl_ddb_entry *ddb =
762 		&crtc_state->wm.skl.plane_ddb[plane_id];
763 	const struct skl_ddb_entry *ddb_y =
764 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
765 	const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];
766 	const u16 *interim_ddb =
767 		&crtc_state->wm.skl.plane_interim_ddb[plane_id];
768 	int level;
769 
770 	for (level = 0; level < display->wm.num_levels; level++)
771 		intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),
772 				   skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
773 
774 	intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),
775 			   skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
776 
777 	if (HAS_HW_SAGV_WM(display)) {
778 		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
779 
780 		intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),
781 				   skl_plane_wm_reg_val(&wm->sagv.wm0));
782 		intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),
783 				   skl_plane_wm_reg_val(&wm->sagv.trans_wm));
784 	}
785 
786 	intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),
787 			   skl_plane_ddb_reg_val(ddb));
788 
789 	if (DISPLAY_VER(display) < 11)
790 		intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),
791 				   skl_plane_ddb_reg_val(ddb_y));
792 
793 	if (DISPLAY_VER(display) >= 30)
794 		intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),
795 				   xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb));
796 }
797 
798 static void
799 skl_plane_disable_arm(struct intel_dsb *dsb,
800 		      struct intel_plane *plane,
801 		      const struct intel_crtc_state *crtc_state)
802 {
803 	struct intel_display *display = to_intel_display(plane->base.dev);
804 	enum plane_id plane_id = plane->id;
805 	enum pipe pipe = plane->pipe;
806 
807 	skl_write_plane_wm(dsb, plane, crtc_state);
808 
809 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
810 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
811 }
812 
813 static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
814 					    struct intel_plane *plane,
815 					    const struct intel_crtc_state *crtc_state)
816 {
817 	struct intel_display *display = to_intel_display(plane->base.dev);
818 	enum pipe pipe = plane->pipe;
819 
820 	if (!crtc_state->enable_psr2_sel_fetch)
821 		return;
822 
823 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
824 }
825 
826 static void
827 icl_plane_disable_arm(struct intel_dsb *dsb,
828 		      struct intel_plane *plane,
829 		      const struct intel_crtc_state *crtc_state)
830 {
831 	struct intel_display *display = to_intel_display(plane->base.dev);
832 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
833 	enum plane_id plane_id = plane->id;
834 	enum pipe pipe = plane->pipe;
835 
836 	if (icl_is_hdr_plane(dev_priv, plane_id))
837 		intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);
838 
839 	skl_write_plane_wm(dsb, plane, crtc_state);
840 
841 	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
842 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
843 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
844 }
845 
846 static bool
847 skl_plane_get_hw_state(struct intel_plane *plane,
848 		       enum pipe *pipe)
849 {
850 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
851 	enum intel_display_power_domain power_domain;
852 	enum plane_id plane_id = plane->id;
853 	intel_wakeref_t wakeref;
854 	bool ret;
855 
856 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
857 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
858 	if (!wakeref)
859 		return false;
860 
861 	ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
862 
863 	*pipe = plane->pipe;
864 
865 	intel_display_power_put(dev_priv, power_domain, wakeref);
866 
867 	return ret;
868 }
869 
870 static u32 skl_plane_ctl_format(u32 pixel_format)
871 {
872 	switch (pixel_format) {
873 	case DRM_FORMAT_C8:
874 		return PLANE_CTL_FORMAT_INDEXED;
875 	case DRM_FORMAT_RGB565:
876 		return PLANE_CTL_FORMAT_RGB_565;
877 	case DRM_FORMAT_XBGR8888:
878 	case DRM_FORMAT_ABGR8888:
879 		return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
880 	case DRM_FORMAT_XRGB8888:
881 	case DRM_FORMAT_ARGB8888:
882 		return PLANE_CTL_FORMAT_XRGB_8888;
883 	case DRM_FORMAT_XBGR2101010:
884 	case DRM_FORMAT_ABGR2101010:
885 		return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
886 	case DRM_FORMAT_XRGB2101010:
887 	case DRM_FORMAT_ARGB2101010:
888 		return PLANE_CTL_FORMAT_XRGB_2101010;
889 	case DRM_FORMAT_XBGR16161616F:
890 	case DRM_FORMAT_ABGR16161616F:
891 		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
892 	case DRM_FORMAT_XRGB16161616F:
893 	case DRM_FORMAT_ARGB16161616F:
894 		return PLANE_CTL_FORMAT_XRGB_16161616F;
895 	case DRM_FORMAT_XYUV8888:
896 		return PLANE_CTL_FORMAT_XYUV;
897 	case DRM_FORMAT_YUYV:
898 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
899 	case DRM_FORMAT_YVYU:
900 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
901 	case DRM_FORMAT_UYVY:
902 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
903 	case DRM_FORMAT_VYUY:
904 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
905 	case DRM_FORMAT_NV12:
906 		return PLANE_CTL_FORMAT_NV12;
907 	case DRM_FORMAT_P010:
908 		return PLANE_CTL_FORMAT_P010;
909 	case DRM_FORMAT_P012:
910 		return PLANE_CTL_FORMAT_P012;
911 	case DRM_FORMAT_P016:
912 		return PLANE_CTL_FORMAT_P016;
913 	case DRM_FORMAT_Y210:
914 		return PLANE_CTL_FORMAT_Y210;
915 	case DRM_FORMAT_Y212:
916 		return PLANE_CTL_FORMAT_Y212;
917 	case DRM_FORMAT_Y216:
918 		return PLANE_CTL_FORMAT_Y216;
919 	case DRM_FORMAT_XVYU2101010:
920 		return PLANE_CTL_FORMAT_Y410;
921 	case DRM_FORMAT_XVYU12_16161616:
922 		return PLANE_CTL_FORMAT_Y412;
923 	case DRM_FORMAT_XVYU16161616:
924 		return PLANE_CTL_FORMAT_Y416;
925 	default:
926 		MISSING_CASE(pixel_format);
927 	}
928 
929 	return 0;
930 }
931 
932 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
933 {
934 	if (!plane_state->hw.fb->format->has_alpha)
935 		return PLANE_CTL_ALPHA_DISABLE;
936 
937 	switch (plane_state->hw.pixel_blend_mode) {
938 	case DRM_MODE_BLEND_PIXEL_NONE:
939 		return PLANE_CTL_ALPHA_DISABLE;
940 	case DRM_MODE_BLEND_PREMULTI:
941 		return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
942 	case DRM_MODE_BLEND_COVERAGE:
943 		return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
944 	default:
945 		MISSING_CASE(plane_state->hw.pixel_blend_mode);
946 		return PLANE_CTL_ALPHA_DISABLE;
947 	}
948 }
949 
950 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
951 {
952 	if (!plane_state->hw.fb->format->has_alpha)
953 		return PLANE_COLOR_ALPHA_DISABLE;
954 
955 	switch (plane_state->hw.pixel_blend_mode) {
956 	case DRM_MODE_BLEND_PIXEL_NONE:
957 		return PLANE_COLOR_ALPHA_DISABLE;
958 	case DRM_MODE_BLEND_PREMULTI:
959 		return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
960 	case DRM_MODE_BLEND_COVERAGE:
961 		return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
962 	default:
963 		MISSING_CASE(plane_state->hw.pixel_blend_mode);
964 		return PLANE_COLOR_ALPHA_DISABLE;
965 	}
966 }
967 
968 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
969 {
970 	switch (fb_modifier) {
971 	case DRM_FORMAT_MOD_LINEAR:
972 		break;
973 	case I915_FORMAT_MOD_X_TILED:
974 		return PLANE_CTL_TILED_X;
975 	case I915_FORMAT_MOD_Y_TILED:
976 		return PLANE_CTL_TILED_Y;
977 	case I915_FORMAT_MOD_4_TILED:
978 		return PLANE_CTL_TILED_4;
979 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
980 		return PLANE_CTL_TILED_4 |
981 			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
982 			PLANE_CTL_CLEAR_COLOR_DISABLE;
983 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
984 		return PLANE_CTL_TILED_4 |
985 			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
986 			PLANE_CTL_CLEAR_COLOR_DISABLE;
987 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
988 		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
989 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
990 		return PLANE_CTL_TILED_4 |
991 			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
992 			PLANE_CTL_CLEAR_COLOR_DISABLE;
993 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
994 		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
995 	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
996 		return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
997 	case I915_FORMAT_MOD_4_TILED_BMG_CCS:
998 	case I915_FORMAT_MOD_4_TILED_LNL_CCS:
999 		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
1000 	case I915_FORMAT_MOD_Y_TILED_CCS:
1001 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1002 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
1003 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1004 		return PLANE_CTL_TILED_Y |
1005 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
1006 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
1007 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1008 		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
1009 	case I915_FORMAT_MOD_Yf_TILED:
1010 		return PLANE_CTL_TILED_YF;
1011 	case I915_FORMAT_MOD_Yf_TILED_CCS:
1012 		return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
1013 	default:
1014 		MISSING_CASE(fb_modifier);
1015 	}
1016 
1017 	return 0;
1018 }
1019 
1020 static u32 skl_plane_ctl_rotate(unsigned int rotate)
1021 {
1022 	switch (rotate) {
1023 	case DRM_MODE_ROTATE_0:
1024 		break;
1025 	/*
1026 	 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
1027 	 * while i915 HW rotation is clockwise, thats why this swapping.
1028 	 */
1029 	case DRM_MODE_ROTATE_90:
1030 		return PLANE_CTL_ROTATE_270;
1031 	case DRM_MODE_ROTATE_180:
1032 		return PLANE_CTL_ROTATE_180;
1033 	case DRM_MODE_ROTATE_270:
1034 		return PLANE_CTL_ROTATE_90;
1035 	default:
1036 		MISSING_CASE(rotate);
1037 	}
1038 
1039 	return 0;
1040 }
1041 
1042 static u32 icl_plane_ctl_flip(unsigned int reflect)
1043 {
1044 	switch (reflect) {
1045 	case 0:
1046 		break;
1047 	case DRM_MODE_REFLECT_X:
1048 		return PLANE_CTL_FLIP_HORIZONTAL;
1049 	case DRM_MODE_REFLECT_Y:
1050 	default:
1051 		MISSING_CASE(reflect);
1052 	}
1053 
1054 	return 0;
1055 }
1056 
1057 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
1058 {
1059 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1060 
1061 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
1062 		switch (fb->format->cpp[0]) {
1063 		case 2:
1064 			return PLANE_CTL_ARB_SLOTS(1);
1065 		default:
1066 			return PLANE_CTL_ARB_SLOTS(0);
1067 		}
1068 	} else {
1069 		switch (fb->format->cpp[0]) {
1070 		case 8:
1071 			return PLANE_CTL_ARB_SLOTS(3);
1072 		case 4:
1073 			return PLANE_CTL_ARB_SLOTS(1);
1074 		default:
1075 			return PLANE_CTL_ARB_SLOTS(0);
1076 		}
1077 	}
1078 }
1079 
1080 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
1081 {
1082 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1083 	u32 plane_ctl = 0;
1084 
1085 	if (DISPLAY_VER(dev_priv) >= 10)
1086 		return plane_ctl;
1087 
1088 	if (crtc_state->gamma_enable)
1089 		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
1090 
1091 	if (crtc_state->csc_enable)
1092 		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
1093 
1094 	return plane_ctl;
1095 }
1096 
1097 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1098 			 const struct intel_plane_state *plane_state)
1099 {
1100 	struct drm_i915_private *dev_priv =
1101 		to_i915(plane_state->uapi.plane->dev);
1102 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1103 	unsigned int rotation = plane_state->hw.rotation;
1104 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1105 	u32 plane_ctl;
1106 
1107 	plane_ctl = PLANE_CTL_ENABLE;
1108 
1109 	if (DISPLAY_VER(dev_priv) < 10) {
1110 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
1111 		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
1112 
1113 		if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1114 			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
1115 
1116 		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1117 			plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
1118 	}
1119 
1120 	plane_ctl |= skl_plane_ctl_format(fb->format->format);
1121 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
1122 	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
1123 
1124 	if (DISPLAY_VER(dev_priv) >= 11)
1125 		plane_ctl |= icl_plane_ctl_flip(rotation &
1126 						DRM_MODE_REFLECT_MASK);
1127 
1128 	if (key->flags & I915_SET_COLORKEY_DESTINATION)
1129 		plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
1130 	else if (key->flags & I915_SET_COLORKEY_SOURCE)
1131 		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
1132 
1133 	/* Wa_22012358565:adl-p */
1134 	if (DISPLAY_VER(dev_priv) == 13)
1135 		plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
1136 
1137 	return plane_ctl;
1138 }
1139 
1140 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
1141 {
1142 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1143 	u32 plane_color_ctl = 0;
1144 
1145 	if (DISPLAY_VER(dev_priv) >= 11)
1146 		return plane_color_ctl;
1147 
1148 	if (crtc_state->gamma_enable)
1149 		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
1150 
1151 	if (crtc_state->csc_enable)
1152 		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
1153 
1154 	return plane_color_ctl;
1155 }
1156 
1157 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1158 			       const struct intel_plane_state *plane_state)
1159 {
1160 	struct drm_i915_private *dev_priv =
1161 		to_i915(plane_state->uapi.plane->dev);
1162 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1163 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1164 	u32 plane_color_ctl = 0;
1165 
1166 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
1167 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
1168 
1169 	if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
1170 		switch (plane_state->hw.color_encoding) {
1171 		case DRM_COLOR_YCBCR_BT709:
1172 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
1173 			break;
1174 		case DRM_COLOR_YCBCR_BT2020:
1175 			plane_color_ctl |=
1176 				PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
1177 			break;
1178 		default:
1179 			plane_color_ctl |=
1180 				PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
1181 		}
1182 		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1183 			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
1184 	} else if (fb->format->is_yuv) {
1185 		plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
1186 		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1187 			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
1188 	}
1189 
1190 	if (plane_state->force_black)
1191 		plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
1192 
1193 	return plane_color_ctl;
1194 }
1195 
1196 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
1197 			    int color_plane)
1198 {
1199 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1200 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1201 	u32 offset = plane_state->view.color_plane[color_plane].offset;
1202 
1203 	if (intel_fb_uses_dpt(fb)) {
1204 		/*
1205 		 * The DPT object contains only one vma, so the VMA's offset
1206 		 * within the DPT is always 0.
1207 		 */
1208 		drm_WARN_ON(&i915->drm, plane_state->dpt_vma &&
1209 			    intel_dpt_offset(plane_state->dpt_vma));
1210 		drm_WARN_ON(&i915->drm, offset & 0x1fffff);
1211 		return offset >> 9;
1212 	} else {
1213 		drm_WARN_ON(&i915->drm, offset & 0xfff);
1214 		return offset;
1215 	}
1216 }
1217 
1218 static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
1219 			  int color_plane)
1220 {
1221 	u32 plane_surf;
1222 
1223 	plane_surf = intel_plane_ggtt_offset(plane_state) +
1224 		skl_surf_address(plane_state, color_plane);
1225 
1226 	if (plane_state->decrypt)
1227 		plane_surf |= PLANE_SURF_DECRYPT;
1228 
1229 	return plane_surf;
1230 }
1231 
1232 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
1233 			      int color_plane)
1234 {
1235 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1236 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1237 	int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1238 	u32 aux_dist;
1239 
1240 	if (!aux_plane)
1241 		return 0;
1242 
1243 	aux_dist = skl_surf_address(plane_state, aux_plane) -
1244 		skl_surf_address(plane_state, color_plane);
1245 
1246 	if (DISPLAY_VER(i915) < 12)
1247 		aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
1248 
1249 	return aux_dist;
1250 }
1251 
1252 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
1253 {
1254 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1255 
1256 	return key->min_value;
1257 }
1258 
1259 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
1260 {
1261 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1262 	u8 alpha = plane_state->hw.alpha >> 8;
1263 
1264 	return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1265 }
1266 
1267 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
1268 {
1269 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1270 	u8 alpha = plane_state->hw.alpha >> 8;
1271 	u32 keymsk;
1272 
1273 	keymsk = key->channel_mask & 0x7ffffff;
1274 	if (alpha < 0xff)
1275 		keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1276 
1277 	return keymsk;
1278 }
1279 
1280 static void icl_plane_csc_load_black(struct intel_dsb *dsb,
1281 				     struct intel_plane *plane,
1282 				     const struct intel_crtc_state *crtc_state)
1283 {
1284 	struct intel_display *display = to_intel_display(plane->base.dev);
1285 	enum plane_id plane_id = plane->id;
1286 	enum pipe pipe = plane->pipe;
1287 
1288 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
1289 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
1290 
1291 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
1292 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
1293 
1294 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
1295 	intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
1296 
1297 	intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
1298 	intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
1299 	intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
1300 
1301 	intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1302 	intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1303 	intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1304 }
1305 
1306 static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1307 {
1308 	/* Program the UV plane on planar master */
1309 	if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1310 		return 1;
1311 	else
1312 		return 0;
1313 }
1314 
1315 static void
1316 skl_plane_update_noarm(struct intel_dsb *dsb,
1317 		       struct intel_plane *plane,
1318 		       const struct intel_crtc_state *crtc_state,
1319 		       const struct intel_plane_state *plane_state)
1320 {
1321 	struct intel_display *display = to_intel_display(plane->base.dev);
1322 	enum plane_id plane_id = plane->id;
1323 	enum pipe pipe = plane->pipe;
1324 	u32 stride = skl_plane_stride(plane_state, 0);
1325 	int crtc_x = plane_state->uapi.dst.x1;
1326 	int crtc_y = plane_state->uapi.dst.y1;
1327 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1328 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1329 
1330 	/* The scaler will handle the output position */
1331 	if (plane_state->scaler_id >= 0) {
1332 		crtc_x = 0;
1333 		crtc_y = 0;
1334 	}
1335 
1336 	intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
1337 			   PLANE_STRIDE_(stride));
1338 	intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
1339 			   PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1340 	intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
1341 			   PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1342 
1343 	skl_write_plane_wm(dsb, plane, crtc_state);
1344 }
1345 
1346 static void
1347 skl_plane_update_arm(struct intel_dsb *dsb,
1348 		     struct intel_plane *plane,
1349 		     const struct intel_crtc_state *crtc_state,
1350 		     const struct intel_plane_state *plane_state)
1351 {
1352 	struct intel_display *display = to_intel_display(plane->base.dev);
1353 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1354 	enum plane_id plane_id = plane->id;
1355 	enum pipe pipe = plane->pipe;
1356 	u32 x = plane_state->view.color_plane[0].x;
1357 	u32 y = plane_state->view.color_plane[0].y;
1358 	u32 plane_ctl, plane_color_ctl = 0;
1359 
1360 	plane_ctl = plane_state->ctl |
1361 		skl_plane_ctl_crtc(crtc_state);
1362 
1363 	/* see intel_plane_atomic_calc_changes() */
1364 	if (plane->need_async_flip_toggle_wa &&
1365 	    crtc_state->async_flip_planes & BIT(plane->id))
1366 		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1367 
1368 	if (DISPLAY_VER(dev_priv) >= 10)
1369 		plane_color_ctl = plane_state->color_ctl |
1370 			glk_plane_color_ctl_crtc(crtc_state);
1371 
1372 	intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
1373 			   skl_plane_keyval(plane_state));
1374 	intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
1375 			   skl_plane_keymsk(plane_state));
1376 	intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
1377 			   skl_plane_keymax(plane_state));
1378 
1379 	intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
1380 			   PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1381 
1382 	intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
1383 			   skl_plane_aux_dist(plane_state, 0));
1384 
1385 	intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),
1386 			   PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
1387 			   PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
1388 
1389 	if (DISPLAY_VER(dev_priv) >= 10)
1390 		intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
1391 				   plane_color_ctl);
1392 
1393 	/*
1394 	 * Enable the scaler before the plane so that we don't
1395 	 * get a catastrophic underrun even if the two operations
1396 	 * end up happening in two different frames.
1397 	 *
1398 	 * TODO: split into noarm+arm pair
1399 	 */
1400 	if (plane_state->scaler_id >= 0)
1401 		skl_program_plane_scaler(plane, crtc_state, plane_state);
1402 
1403 	/*
1404 	 * The control register self-arms if the plane was previously
1405 	 * disabled. Try to make the plane enable atomic by writing
1406 	 * the control register just before the surface register.
1407 	 */
1408 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1409 			   plane_ctl);
1410 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1411 			   skl_plane_surf(plane_state, 0));
1412 }
1413 
1414 static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb,
1415 					     struct intel_plane *plane,
1416 					     const struct intel_crtc_state *crtc_state,
1417 					     const struct intel_plane_state *plane_state,
1418 					     int color_plane)
1419 {
1420 	struct intel_display *display = to_intel_display(plane->base.dev);
1421 	enum pipe pipe = plane->pipe;
1422 	const struct drm_rect *clip;
1423 	u32 val;
1424 	int x, y;
1425 
1426 	if (!crtc_state->enable_psr2_sel_fetch)
1427 		return;
1428 
1429 	clip = &plane_state->psr2_sel_fetch_area;
1430 
1431 	if (crtc_state->enable_psr2_su_region_et)
1432 		y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1);
1433 	else
1434 		y = (clip->y1 + plane_state->uapi.dst.y1);
1435 	val = y << 16;
1436 	val |= plane_state->uapi.dst.x1;
1437 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
1438 
1439 	x = plane_state->view.color_plane[color_plane].x;
1440 
1441 	/*
1442 	 * From Bspec: UV surface Start Y Position = half of Y plane Y
1443 	 * start position.
1444 	 */
1445 	if (!color_plane)
1446 		y = plane_state->view.color_plane[color_plane].y + clip->y1;
1447 	else
1448 		y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1449 
1450 	val = y << 16 | x;
1451 
1452 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);
1453 
1454 	/* Sizes are 0 based */
1455 	val = (drm_rect_height(clip) - 1) << 16;
1456 	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1457 	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
1458 }
1459 
1460 static void
1461 icl_plane_update_noarm(struct intel_dsb *dsb,
1462 		       struct intel_plane *plane,
1463 		       const struct intel_crtc_state *crtc_state,
1464 		       const struct intel_plane_state *plane_state)
1465 {
1466 	struct intel_display *display = to_intel_display(plane->base.dev);
1467 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1468 	enum plane_id plane_id = plane->id;
1469 	enum pipe pipe = plane->pipe;
1470 	int color_plane = icl_plane_color_plane(plane_state);
1471 	u32 stride = skl_plane_stride(plane_state, color_plane);
1472 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1473 	int crtc_x = plane_state->uapi.dst.x1;
1474 	int crtc_y = plane_state->uapi.dst.y1;
1475 	int x = plane_state->view.color_plane[color_plane].x;
1476 	int y = plane_state->view.color_plane[color_plane].y;
1477 	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1478 	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1479 	u32 plane_color_ctl;
1480 
1481 	plane_color_ctl = plane_state->color_ctl |
1482 		glk_plane_color_ctl_crtc(crtc_state);
1483 
1484 	/* The scaler will handle the output position */
1485 	if (plane_state->scaler_id >= 0) {
1486 		crtc_x = 0;
1487 		crtc_y = 0;
1488 	}
1489 
1490 	intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
1491 			   PLANE_STRIDE_(stride));
1492 	intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
1493 			   PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1494 	intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
1495 			   PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1496 
1497 	intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
1498 			   skl_plane_keyval(plane_state));
1499 	intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
1500 			   skl_plane_keymsk(plane_state));
1501 	intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
1502 			   skl_plane_keymax(plane_state));
1503 
1504 	intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
1505 			   PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1506 
1507 	if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
1508 		intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),
1509 				   lower_32_bits(plane_state->ccval));
1510 		intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),
1511 				   upper_32_bits(plane_state->ccval));
1512 	}
1513 
1514 	/* FLAT CCS doesn't need to program AUX_DIST */
1515 	if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
1516 		intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
1517 				   skl_plane_aux_dist(plane_state, color_plane));
1518 
1519 	if (icl_is_hdr_plane(dev_priv, plane_id))
1520 		intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),
1521 				   plane_state->cus_ctl);
1522 
1523 	intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
1524 			   plane_color_ctl);
1525 
1526 	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
1527 		icl_program_input_csc(dsb, plane, plane_state);
1528 
1529 	skl_write_plane_wm(dsb, plane, crtc_state);
1530 
1531 	/*
1532 	 * FIXME: pxp session invalidation can hit any time even at time of commit
1533 	 * or after the commit, display content will be garbage.
1534 	 */
1535 	if (plane_state->force_black)
1536 		icl_plane_csc_load_black(dsb, plane, crtc_state);
1537 
1538 	icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);
1539 }
1540 
1541 static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb,
1542 					   struct intel_plane *plane,
1543 					   const struct intel_crtc_state *crtc_state,
1544 					   const struct intel_plane_state *plane_state)
1545 {
1546 	struct intel_display *display = to_intel_display(plane->base.dev);
1547 	enum pipe pipe = plane->pipe;
1548 
1549 	if (!crtc_state->enable_psr2_sel_fetch)
1550 		return;
1551 
1552 	if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
1553 		intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),
1554 				   SEL_FETCH_PLANE_CTL_ENABLE);
1555 	else
1556 		icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
1557 }
1558 
1559 static void
1560 icl_plane_update_arm(struct intel_dsb *dsb,
1561 		     struct intel_plane *plane,
1562 		     const struct intel_crtc_state *crtc_state,
1563 		     const struct intel_plane_state *plane_state)
1564 {
1565 	struct intel_display *display = to_intel_display(plane->base.dev);
1566 	enum plane_id plane_id = plane->id;
1567 	enum pipe pipe = plane->pipe;
1568 	int color_plane = icl_plane_color_plane(plane_state);
1569 	u32 plane_ctl;
1570 
1571 	plane_ctl = plane_state->ctl |
1572 		skl_plane_ctl_crtc(crtc_state);
1573 
1574 	/*
1575 	 * Enable the scaler before the plane so that we don't
1576 	 * get a catastrophic underrun even if the two operations
1577 	 * end up happening in two different frames.
1578 	 *
1579 	 * TODO: split into noarm+arm pair
1580 	 */
1581 	if (plane_state->scaler_id >= 0)
1582 		skl_program_plane_scaler(plane, crtc_state, plane_state);
1583 
1584 	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
1585 
1586 	/*
1587 	 * The control register self-arms if the plane was previously
1588 	 * disabled. Try to make the plane enable atomic by writing
1589 	 * the control register just before the surface register.
1590 	 */
1591 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1592 			   plane_ctl);
1593 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1594 			   skl_plane_surf(plane_state, color_plane));
1595 }
1596 
1597 static void
1598 skl_plane_async_flip(struct intel_dsb *dsb,
1599 		     struct intel_plane *plane,
1600 		     const struct intel_crtc_state *crtc_state,
1601 		     const struct intel_plane_state *plane_state,
1602 		     bool async_flip)
1603 {
1604 	struct intel_display *display = to_intel_display(plane->base.dev);
1605 	enum plane_id plane_id = plane->id;
1606 	enum pipe pipe = plane->pipe;
1607 	u32 plane_ctl = plane_state->ctl, plane_surf;
1608 
1609 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1610 	plane_surf = skl_plane_surf(plane_state, 0);
1611 
1612 	if (async_flip) {
1613 		if (DISPLAY_VER(display) >= 30)
1614 			plane_surf |= PLANE_SURF_ASYNC_UPDATE;
1615 		else
1616 			plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1617 	}
1618 
1619 	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1620 			   plane_ctl);
1621 	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1622 			   plane_surf);
1623 }
1624 
1625 static bool intel_format_is_p01x(u32 format)
1626 {
1627 	switch (format) {
1628 	case DRM_FORMAT_P010:
1629 	case DRM_FORMAT_P012:
1630 	case DRM_FORMAT_P016:
1631 		return true;
1632 	default:
1633 		return false;
1634 	}
1635 }
1636 
1637 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1638 			      const struct intel_plane_state *plane_state)
1639 {
1640 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1641 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1642 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1643 	unsigned int rotation = plane_state->hw.rotation;
1644 
1645 	if (!fb)
1646 		return 0;
1647 
1648 	if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1649 	    intel_fb_is_ccs_modifier(fb->modifier)) {
1650 		drm_dbg_kms(&dev_priv->drm,
1651 			    "RC support only with 0/180 degree rotation (%x)\n",
1652 			    rotation);
1653 		return -EINVAL;
1654 	}
1655 
1656 	if (rotation & DRM_MODE_REFLECT_X &&
1657 	    fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1658 		drm_dbg_kms(&dev_priv->drm,
1659 			    "horizontal flip is not supported with linear surface formats\n");
1660 		return -EINVAL;
1661 	}
1662 
1663 	/*
1664 	 * Display20 onward tile4 hflip is not supported
1665 	 */
1666 	if (rotation & DRM_MODE_REFLECT_X &&
1667 	    intel_fb_is_tile4_modifier(fb->modifier) &&
1668 	    DISPLAY_VER(dev_priv) >= 20) {
1669 		drm_dbg_kms(&dev_priv->drm,
1670 			    "horizontal flip is not supported with tile4 surface formats\n");
1671 		return -EINVAL;
1672 	}
1673 
1674 	if (drm_rotation_90_or_270(rotation)) {
1675 		if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
1676 			drm_dbg_kms(&dev_priv->drm,
1677 				    "Y/Yf tiling required for 90/270!\n");
1678 			return -EINVAL;
1679 		}
1680 
1681 		/*
1682 		 * 90/270 is not allowed with RGB64 16:16:16:16 and
1683 		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1684 		 */
1685 		switch (fb->format->format) {
1686 		case DRM_FORMAT_RGB565:
1687 			if (DISPLAY_VER(dev_priv) >= 11)
1688 				break;
1689 			fallthrough;
1690 		case DRM_FORMAT_C8:
1691 		case DRM_FORMAT_XRGB16161616F:
1692 		case DRM_FORMAT_XBGR16161616F:
1693 		case DRM_FORMAT_ARGB16161616F:
1694 		case DRM_FORMAT_ABGR16161616F:
1695 		case DRM_FORMAT_Y210:
1696 		case DRM_FORMAT_Y212:
1697 		case DRM_FORMAT_Y216:
1698 		case DRM_FORMAT_XVYU12_16161616:
1699 		case DRM_FORMAT_XVYU16161616:
1700 			drm_dbg_kms(&dev_priv->drm,
1701 				    "Unsupported pixel format %p4cc for 90/270!\n",
1702 				    &fb->format->format);
1703 			return -EINVAL;
1704 		default:
1705 			break;
1706 		}
1707 	}
1708 
1709 	/* Y-tiling is not supported in IF-ID Interlace mode */
1710 	if (crtc_state->hw.enable &&
1711 	    crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1712 	    fb->modifier != DRM_FORMAT_MOD_LINEAR &&
1713 	    fb->modifier != I915_FORMAT_MOD_X_TILED) {
1714 		drm_dbg_kms(&dev_priv->drm,
1715 			    "Y/Yf tiling not supported in IF-ID mode\n");
1716 		return -EINVAL;
1717 	}
1718 
1719 	/* Wa_1606054188:tgl,adl-s */
1720 	if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
1721 	    plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
1722 	    intel_format_is_p01x(fb->format->format)) {
1723 		drm_dbg_kms(&dev_priv->drm,
1724 			    "Source color keying not supported with P01x formats\n");
1725 		return -EINVAL;
1726 	}
1727 
1728 	return 0;
1729 }
1730 
1731 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1732 					   const struct intel_plane_state *plane_state)
1733 {
1734 	struct drm_i915_private *dev_priv =
1735 		to_i915(plane_state->uapi.plane->dev);
1736 	int crtc_x = plane_state->uapi.dst.x1;
1737 	int crtc_w = drm_rect_width(&plane_state->uapi.dst);
1738 	int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
1739 
1740 	/*
1741 	 * Display WA #1175: glk
1742 	 * Planes other than the cursor may cause FIFO underflow and display
1743 	 * corruption if starting less than 4 pixels from the right edge of
1744 	 * the screen.
1745 	 * Besides the above WA fix the similar problem, where planes other
1746 	 * than the cursor ending less than 4 pixels from the left edge of the
1747 	 * screen may cause FIFO underflow and display corruption.
1748 	 */
1749 	if (DISPLAY_VER(dev_priv) == 10 &&
1750 	    (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1751 		drm_dbg_kms(&dev_priv->drm,
1752 			    "requested plane X %s position %d invalid (valid range %d-%d)\n",
1753 			    crtc_x + crtc_w < 4 ? "end" : "start",
1754 			    crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1755 			    4, pipe_src_w - 4);
1756 		return -ERANGE;
1757 	}
1758 
1759 	return 0;
1760 }
1761 
1762 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1763 {
1764 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1765 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1766 	unsigned int rotation = plane_state->hw.rotation;
1767 	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1768 
1769 	/* Display WA #1106 */
1770 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1771 	    src_w & 3 &&
1772 	    (rotation == DRM_MODE_ROTATE_270 ||
1773 	     rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1774 		drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
1775 		return -EINVAL;
1776 	}
1777 
1778 	return 0;
1779 }
1780 
1781 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
1782 			       const struct drm_framebuffer *fb)
1783 {
1784 	/*
1785 	 * We don't yet know the final source width nor
1786 	 * whether we can use the HQ scaler mode. Assume
1787 	 * the best case.
1788 	 * FIXME need to properly check this later.
1789 	 */
1790 	if (DISPLAY_VER(dev_priv) >= 10 ||
1791 	    !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1792 		return 0x30000 - 1;
1793 	else
1794 		return 0x20000 - 1;
1795 }
1796 
1797 static int intel_plane_min_width(struct intel_plane *plane,
1798 				 const struct drm_framebuffer *fb,
1799 				 int color_plane,
1800 				 unsigned int rotation)
1801 {
1802 	if (plane->min_width)
1803 		return plane->min_width(fb, color_plane, rotation);
1804 	else
1805 		return 1;
1806 }
1807 
1808 static int intel_plane_max_width(struct intel_plane *plane,
1809 				 const struct drm_framebuffer *fb,
1810 				 int color_plane,
1811 				 unsigned int rotation)
1812 {
1813 	if (plane->max_width)
1814 		return plane->max_width(fb, color_plane, rotation);
1815 	else
1816 		return INT_MAX;
1817 }
1818 
1819 static int intel_plane_max_height(struct intel_plane *plane,
1820 				  const struct drm_framebuffer *fb,
1821 				  int color_plane,
1822 				  unsigned int rotation)
1823 {
1824 	if (plane->max_height)
1825 		return plane->max_height(fb, color_plane, rotation);
1826 	else
1827 		return INT_MAX;
1828 }
1829 
1830 static bool
1831 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
1832 			       int main_x, int main_y, u32 main_offset,
1833 			       int ccs_plane)
1834 {
1835 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1836 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1837 	int aux_x = plane_state->view.color_plane[ccs_plane].x;
1838 	int aux_y = plane_state->view.color_plane[ccs_plane].y;
1839 	u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1840 	unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane);
1841 	int hsub;
1842 	int vsub;
1843 
1844 	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1845 	while (aux_offset >= main_offset && aux_y <= main_y) {
1846 		int x, y;
1847 
1848 		if (aux_x == main_x && aux_y == main_y)
1849 			break;
1850 
1851 		if (aux_offset == 0)
1852 			break;
1853 
1854 		x = aux_x / hsub;
1855 		y = aux_y / vsub;
1856 		aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
1857 							       plane_state,
1858 							       ccs_plane,
1859 							       aux_offset,
1860 							       aux_offset - alignment);
1861 		aux_x = x * hsub + aux_x % hsub;
1862 		aux_y = y * vsub + aux_y % vsub;
1863 	}
1864 
1865 	if (aux_x != main_x || aux_y != main_y)
1866 		return false;
1867 
1868 	plane_state->view.color_plane[ccs_plane].offset = aux_offset;
1869 	plane_state->view.color_plane[ccs_plane].x = aux_x;
1870 	plane_state->view.color_plane[ccs_plane].y = aux_y;
1871 
1872 	return true;
1873 }
1874 
1875 
1876 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
1877 				 int *x, int *y, u32 *offset)
1878 {
1879 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1880 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1881 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1882 	int aux_plane = skl_main_to_aux_plane(fb, 0);
1883 	u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;
1884 	unsigned int alignment = plane->min_alignment(plane, fb, 0);
1885 	int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1886 
1887 	intel_add_fb_offsets(x, y, plane_state, 0);
1888 	*offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
1889 	if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
1890 		return -EINVAL;
1891 
1892 	/*
1893 	 * AUX surface offset is specified as the distance from the
1894 	 * main surface offset, and it must be non-negative. Make
1895 	 * sure that is what we will get.
1896 	 */
1897 	if (aux_plane && *offset > aux_offset)
1898 		*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1899 							    *offset,
1900 							    aux_offset & ~(alignment - 1));
1901 
1902 	/*
1903 	 * When using an X-tiled surface, the plane blows up
1904 	 * if the x offset + width exceed the stride.
1905 	 *
1906 	 * TODO: linear and Y-tiled seem fine, Yf untested,
1907 	 */
1908 	if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
1909 		int cpp = fb->format->cpp[0];
1910 
1911 		while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
1912 			if (*offset == 0) {
1913 				drm_dbg_kms(&dev_priv->drm,
1914 					    "Unable to find suitable display surface offset due to X-tiling\n");
1915 				return -EINVAL;
1916 			}
1917 
1918 			*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1919 								    *offset,
1920 								    *offset - alignment);
1921 		}
1922 	}
1923 
1924 	return 0;
1925 }
1926 
1927 static int skl_check_main_surface(struct intel_plane_state *plane_state)
1928 {
1929 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1930 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1931 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1932 	unsigned int rotation = plane_state->hw.rotation;
1933 	int x = plane_state->uapi.src.x1 >> 16;
1934 	int y = plane_state->uapi.src.y1 >> 16;
1935 	int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1936 	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
1937 	int min_width = intel_plane_min_width(plane, fb, 0, rotation);
1938 	int max_width = intel_plane_max_width(plane, fb, 0, rotation);
1939 	int max_height = intel_plane_max_height(plane, fb, 0, rotation);
1940 	unsigned int alignment = plane->min_alignment(plane, fb, 0);
1941 	int aux_plane = skl_main_to_aux_plane(fb, 0);
1942 	u32 offset;
1943 	int ret;
1944 
1945 	if (w > max_width || w < min_width || h > max_height || h < 1) {
1946 		drm_dbg_kms(&dev_priv->drm,
1947 			    "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
1948 			    w, h, min_width, max_width, max_height);
1949 		return -EINVAL;
1950 	}
1951 
1952 	ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1953 	if (ret)
1954 		return ret;
1955 
1956 	/*
1957 	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
1958 	 * they match with the main surface x/y offsets. On DG2
1959 	 * there's no aux plane on fb so skip this checking.
1960 	 */
1961 	if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
1962 		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1963 						       offset, aux_plane)) {
1964 			if (offset == 0)
1965 				break;
1966 
1967 			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1968 								   offset, offset - alignment);
1969 		}
1970 
1971 		if (x != plane_state->view.color_plane[aux_plane].x ||
1972 		    y != plane_state->view.color_plane[aux_plane].y) {
1973 			drm_dbg_kms(&dev_priv->drm,
1974 				    "Unable to find suitable display surface offset due to CCS\n");
1975 			return -EINVAL;
1976 		}
1977 	}
1978 
1979 	if (DISPLAY_VER(dev_priv) >= 13)
1980 		drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
1981 	else
1982 		drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
1983 
1984 	plane_state->view.color_plane[0].offset = offset;
1985 	plane_state->view.color_plane[0].x = x;
1986 	plane_state->view.color_plane[0].y = y;
1987 
1988 	/*
1989 	 * Put the final coordinates back so that the src
1990 	 * coordinate checks will see the right values.
1991 	 */
1992 	drm_rect_translate_to(&plane_state->uapi.src,
1993 			      x << 16, y << 16);
1994 
1995 	return 0;
1996 }
1997 
1998 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
1999 {
2000 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2001 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
2002 	const struct drm_framebuffer *fb = plane_state->hw.fb;
2003 	unsigned int rotation = plane_state->hw.rotation;
2004 	int uv_plane = 1;
2005 	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
2006 			skl_main_to_aux_plane(fb, uv_plane) : 0;
2007 	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
2008 	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
2009 	int x = plane_state->uapi.src.x1 >> 17;
2010 	int y = plane_state->uapi.src.y1 >> 17;
2011 	int w = drm_rect_width(&plane_state->uapi.src) >> 17;
2012 	int h = drm_rect_height(&plane_state->uapi.src) >> 17;
2013 	u32 offset;
2014 
2015 	/* FIXME not quite sure how/if these apply to the chroma plane */
2016 	if (w > max_width || h > max_height) {
2017 		drm_dbg_kms(&i915->drm,
2018 			    "CbCr source size %dx%d too big (limit %dx%d)\n",
2019 			    w, h, max_width, max_height);
2020 		return -EINVAL;
2021 	}
2022 
2023 	intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
2024 	offset = intel_plane_compute_aligned_offset(&x, &y,
2025 						    plane_state, uv_plane);
2026 
2027 	if (ccs_plane) {
2028 		u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
2029 		unsigned int alignment = plane->min_alignment(plane, fb, uv_plane);
2030 
2031 		if (offset > aux_offset)
2032 			offset = intel_plane_adjust_aligned_offset(&x, &y,
2033 								   plane_state,
2034 								   uv_plane,
2035 								   offset,
2036 								   aux_offset & ~(alignment - 1));
2037 
2038 		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
2039 						       offset, ccs_plane)) {
2040 			if (offset == 0)
2041 				break;
2042 
2043 			offset = intel_plane_adjust_aligned_offset(&x, &y,
2044 								   plane_state,
2045 								   uv_plane,
2046 								   offset, offset - alignment);
2047 		}
2048 
2049 		if (x != plane_state->view.color_plane[ccs_plane].x ||
2050 		    y != plane_state->view.color_plane[ccs_plane].y) {
2051 			drm_dbg_kms(&i915->drm,
2052 				    "Unable to find suitable display surface offset due to CCS\n");
2053 			return -EINVAL;
2054 		}
2055 	}
2056 
2057 	if (DISPLAY_VER(i915) >= 13)
2058 		drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
2059 	else
2060 		drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
2061 
2062 	plane_state->view.color_plane[uv_plane].offset = offset;
2063 	plane_state->view.color_plane[uv_plane].x = x;
2064 	plane_state->view.color_plane[uv_plane].y = y;
2065 
2066 	return 0;
2067 }
2068 
2069 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
2070 {
2071 	const struct drm_framebuffer *fb = plane_state->hw.fb;
2072 	int src_x = plane_state->uapi.src.x1 >> 16;
2073 	int src_y = plane_state->uapi.src.y1 >> 16;
2074 	u32 offset;
2075 	int ccs_plane;
2076 
2077 	for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
2078 		int main_hsub, main_vsub;
2079 		int hsub, vsub;
2080 		int x, y;
2081 
2082 		if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
2083 			continue;
2084 
2085 		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
2086 					       skl_ccs_to_main_plane(fb, ccs_plane));
2087 		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2088 
2089 		hsub *= main_hsub;
2090 		vsub *= main_vsub;
2091 		x = src_x / hsub;
2092 		y = src_y / vsub;
2093 
2094 		intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
2095 
2096 		offset = intel_plane_compute_aligned_offset(&x, &y,
2097 							    plane_state,
2098 							    ccs_plane);
2099 
2100 		plane_state->view.color_plane[ccs_plane].offset = offset;
2101 		plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;
2102 		plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;
2103 	}
2104 
2105 	return 0;
2106 }
2107 
2108 static int skl_check_plane_surface(struct intel_plane_state *plane_state)
2109 {
2110 	const struct drm_framebuffer *fb = plane_state->hw.fb;
2111 	int ret;
2112 
2113 	ret = intel_plane_compute_gtt(plane_state);
2114 	if (ret)
2115 		return ret;
2116 
2117 	if (!plane_state->uapi.visible)
2118 		return 0;
2119 
2120 	/*
2121 	 * Handle the AUX surface first since the main surface setup depends on
2122 	 * it.
2123 	 */
2124 	if (intel_fb_is_ccs_modifier(fb->modifier)) {
2125 		ret = skl_check_ccs_aux_surface(plane_state);
2126 		if (ret)
2127 			return ret;
2128 	}
2129 
2130 	if (intel_format_info_is_yuv_semiplanar(fb->format,
2131 						fb->modifier)) {
2132 		ret = skl_check_nv12_aux_surface(plane_state);
2133 		if (ret)
2134 			return ret;
2135 	}
2136 
2137 	ret = skl_check_main_surface(plane_state);
2138 	if (ret)
2139 		return ret;
2140 
2141 	return 0;
2142 }
2143 
2144 static bool skl_fb_scalable(const struct drm_framebuffer *fb)
2145 {
2146 	if (!fb)
2147 		return false;
2148 
2149 	switch (fb->format->format) {
2150 	case DRM_FORMAT_C8:
2151 		return false;
2152 	case DRM_FORMAT_XRGB16161616F:
2153 	case DRM_FORMAT_ARGB16161616F:
2154 	case DRM_FORMAT_XBGR16161616F:
2155 	case DRM_FORMAT_ABGR16161616F:
2156 		return DISPLAY_VER(to_i915(fb->dev)) >= 11;
2157 	default:
2158 		return true;
2159 	}
2160 }
2161 
2162 static void check_protection(struct intel_plane_state *plane_state)
2163 {
2164 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2165 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
2166 	const struct drm_framebuffer *fb = plane_state->hw.fb;
2167 	struct drm_gem_object *obj = intel_fb_bo(fb);
2168 
2169 	if (DISPLAY_VER(i915) < 11)
2170 		return;
2171 
2172 	plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0;
2173 	plane_state->force_black = intel_bo_is_protected(obj) &&
2174 		!plane_state->decrypt;
2175 }
2176 
2177 static int skl_plane_check(struct intel_crtc_state *crtc_state,
2178 			   struct intel_plane_state *plane_state)
2179 {
2180 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2181 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2182 	const struct drm_framebuffer *fb = plane_state->hw.fb;
2183 	int min_scale = DRM_PLANE_NO_SCALING;
2184 	int max_scale = DRM_PLANE_NO_SCALING;
2185 	int ret;
2186 
2187 	ret = skl_plane_check_fb(crtc_state, plane_state);
2188 	if (ret)
2189 		return ret;
2190 
2191 	/* use scaler when colorkey is not required */
2192 	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
2193 		min_scale = 1;
2194 		max_scale = skl_plane_max_scale(dev_priv, fb);
2195 	}
2196 
2197 	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
2198 						min_scale, max_scale, true);
2199 	if (ret)
2200 		return ret;
2201 
2202 	ret = skl_check_plane_surface(plane_state);
2203 	if (ret)
2204 		return ret;
2205 
2206 	if (!plane_state->uapi.visible)
2207 		return 0;
2208 
2209 	ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
2210 	if (ret)
2211 		return ret;
2212 
2213 	ret = intel_plane_check_src_coordinates(plane_state);
2214 	if (ret)
2215 		return ret;
2216 
2217 	ret = skl_plane_check_nv12_rotation(plane_state);
2218 	if (ret)
2219 		return ret;
2220 
2221 	check_protection(plane_state);
2222 
2223 	/* HW only has 8 bits pixel precision, disable plane if invisible */
2224 	if (!(plane_state->hw.alpha >> 8))
2225 		plane_state->uapi.visible = false;
2226 
2227 	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
2228 
2229 	if (DISPLAY_VER(dev_priv) >= 10)
2230 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
2231 							     plane_state);
2232 
2233 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2234 	    icl_is_hdr_plane(dev_priv, plane->id))
2235 		/* Enable and use MPEG-2 chroma siting */
2236 		plane_state->cus_ctl = PLANE_CUS_ENABLE |
2237 			PLANE_CUS_HPHASE_0 |
2238 			PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
2239 	else
2240 		plane_state->cus_ctl = 0;
2241 
2242 	return 0;
2243 }
2244 
2245 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
2246 {
2247 	return pipe - PIPE_A + INTEL_FBC_A;
2248 }
2249 
2250 static bool skl_plane_has_fbc(struct drm_i915_private *i915,
2251 			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
2252 {
2253 	if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0)
2254 		return false;
2255 
2256 	if (DISPLAY_VER(i915) >= 20)
2257 		return icl_is_hdr_plane(i915, plane_id);
2258 	else
2259 		return plane_id == PLANE_1;
2260 }
2261 
2262 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
2263 				       enum pipe pipe, enum plane_id plane_id)
2264 {
2265 	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
2266 
2267 	if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
2268 		return dev_priv->display.fbc[fbc_id];
2269 	else
2270 		return NULL;
2271 }
2272 
2273 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2274 				 enum pipe pipe, enum plane_id plane_id)
2275 {
2276 	/* Display WA #0870: skl, bxt */
2277 	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
2278 		return false;
2279 
2280 	if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
2281 		return false;
2282 
2283 	if (plane_id != PLANE_1 && plane_id != PLANE_2)
2284 		return false;
2285 
2286 	return true;
2287 }
2288 
2289 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
2290 					enum pipe pipe, enum plane_id plane_id,
2291 					int *num_formats)
2292 {
2293 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2294 		*num_formats = ARRAY_SIZE(skl_planar_formats);
2295 		return skl_planar_formats;
2296 	} else {
2297 		*num_formats = ARRAY_SIZE(skl_plane_formats);
2298 		return skl_plane_formats;
2299 	}
2300 }
2301 
2302 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
2303 					enum pipe pipe, enum plane_id plane_id,
2304 					int *num_formats)
2305 {
2306 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2307 		*num_formats = ARRAY_SIZE(glk_planar_formats);
2308 		return glk_planar_formats;
2309 	} else {
2310 		*num_formats = ARRAY_SIZE(skl_plane_formats);
2311 		return skl_plane_formats;
2312 	}
2313 }
2314 
2315 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2316 					enum pipe pipe, enum plane_id plane_id,
2317 					int *num_formats)
2318 {
2319 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
2320 		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2321 		return icl_hdr_plane_formats;
2322 	} else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
2323 		*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2324 		return icl_sdr_y_plane_formats;
2325 	} else {
2326 		*num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2327 		return icl_sdr_uv_plane_formats;
2328 	}
2329 }
2330 
2331 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2332 					   u32 format, u64 modifier)
2333 {
2334 	struct intel_plane *plane = to_intel_plane(_plane);
2335 
2336 	if (!intel_fb_plane_supports_modifier(plane, modifier))
2337 		return false;
2338 
2339 	switch (format) {
2340 	case DRM_FORMAT_XRGB8888:
2341 	case DRM_FORMAT_XBGR8888:
2342 	case DRM_FORMAT_ARGB8888:
2343 	case DRM_FORMAT_ABGR8888:
2344 		if (intel_fb_is_ccs_modifier(modifier))
2345 			return true;
2346 		fallthrough;
2347 	case DRM_FORMAT_RGB565:
2348 	case DRM_FORMAT_XRGB2101010:
2349 	case DRM_FORMAT_XBGR2101010:
2350 	case DRM_FORMAT_ARGB2101010:
2351 	case DRM_FORMAT_ABGR2101010:
2352 	case DRM_FORMAT_YUYV:
2353 	case DRM_FORMAT_YVYU:
2354 	case DRM_FORMAT_UYVY:
2355 	case DRM_FORMAT_VYUY:
2356 	case DRM_FORMAT_NV12:
2357 	case DRM_FORMAT_XYUV8888:
2358 	case DRM_FORMAT_P010:
2359 	case DRM_FORMAT_P012:
2360 	case DRM_FORMAT_P016:
2361 	case DRM_FORMAT_XVYU2101010:
2362 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
2363 			return true;
2364 		fallthrough;
2365 	case DRM_FORMAT_C8:
2366 	case DRM_FORMAT_XBGR16161616F:
2367 	case DRM_FORMAT_ABGR16161616F:
2368 	case DRM_FORMAT_XRGB16161616F:
2369 	case DRM_FORMAT_ARGB16161616F:
2370 	case DRM_FORMAT_Y210:
2371 	case DRM_FORMAT_Y212:
2372 	case DRM_FORMAT_Y216:
2373 	case DRM_FORMAT_XVYU12_16161616:
2374 	case DRM_FORMAT_XVYU16161616:
2375 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
2376 		    modifier == I915_FORMAT_MOD_X_TILED ||
2377 		    modifier == I915_FORMAT_MOD_Y_TILED)
2378 			return true;
2379 		fallthrough;
2380 	default:
2381 		return false;
2382 	}
2383 }
2384 
2385 static bool icl_plane_format_mod_supported(struct drm_plane *_plane,
2386 					   u32 format, u64 modifier)
2387 {
2388 	struct intel_plane *plane = to_intel_plane(_plane);
2389 
2390 	if (!intel_fb_plane_supports_modifier(plane, modifier))
2391 		return false;
2392 
2393 	switch (format) {
2394 	case DRM_FORMAT_XRGB8888:
2395 	case DRM_FORMAT_XBGR8888:
2396 	case DRM_FORMAT_ARGB8888:
2397 	case DRM_FORMAT_ABGR8888:
2398 	case DRM_FORMAT_XRGB2101010:
2399 	case DRM_FORMAT_XBGR2101010:
2400 	case DRM_FORMAT_ARGB2101010:
2401 	case DRM_FORMAT_ABGR2101010:
2402 		if (intel_fb_is_ccs_modifier(modifier))
2403 			return true;
2404 		fallthrough;
2405 	case DRM_FORMAT_RGB565:
2406 	case DRM_FORMAT_YUYV:
2407 	case DRM_FORMAT_YVYU:
2408 	case DRM_FORMAT_UYVY:
2409 	case DRM_FORMAT_VYUY:
2410 	case DRM_FORMAT_NV12:
2411 	case DRM_FORMAT_XYUV8888:
2412 	case DRM_FORMAT_P010:
2413 	case DRM_FORMAT_P012:
2414 	case DRM_FORMAT_P016:
2415 	case DRM_FORMAT_XVYU2101010:
2416 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
2417 			return true;
2418 		fallthrough;
2419 	case DRM_FORMAT_C8:
2420 	case DRM_FORMAT_XBGR16161616F:
2421 	case DRM_FORMAT_ABGR16161616F:
2422 	case DRM_FORMAT_XRGB16161616F:
2423 	case DRM_FORMAT_ARGB16161616F:
2424 	case DRM_FORMAT_Y210:
2425 	case DRM_FORMAT_Y212:
2426 	case DRM_FORMAT_Y216:
2427 	case DRM_FORMAT_XVYU12_16161616:
2428 	case DRM_FORMAT_XVYU16161616:
2429 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
2430 		    modifier == I915_FORMAT_MOD_X_TILED ||
2431 		    modifier == I915_FORMAT_MOD_Y_TILED)
2432 			return true;
2433 		fallthrough;
2434 	default:
2435 		return false;
2436 	}
2437 }
2438 
2439 static bool tgl_plane_format_mod_supported(struct drm_plane *_plane,
2440 					   u32 format, u64 modifier)
2441 {
2442 	struct intel_plane *plane = to_intel_plane(_plane);
2443 
2444 	if (!intel_fb_plane_supports_modifier(plane, modifier))
2445 		return false;
2446 
2447 	switch (format) {
2448 	case DRM_FORMAT_XRGB8888:
2449 	case DRM_FORMAT_XBGR8888:
2450 	case DRM_FORMAT_ARGB8888:
2451 	case DRM_FORMAT_ABGR8888:
2452 	case DRM_FORMAT_XRGB2101010:
2453 	case DRM_FORMAT_XBGR2101010:
2454 	case DRM_FORMAT_ARGB2101010:
2455 	case DRM_FORMAT_ABGR2101010:
2456 	case DRM_FORMAT_XBGR16161616F:
2457 	case DRM_FORMAT_ABGR16161616F:
2458 	case DRM_FORMAT_XRGB16161616F:
2459 	case DRM_FORMAT_ARGB16161616F:
2460 		if (intel_fb_is_ccs_modifier(modifier))
2461 			return true;
2462 		fallthrough;
2463 	case DRM_FORMAT_YUYV:
2464 	case DRM_FORMAT_YVYU:
2465 	case DRM_FORMAT_UYVY:
2466 	case DRM_FORMAT_VYUY:
2467 	case DRM_FORMAT_NV12:
2468 	case DRM_FORMAT_XYUV8888:
2469 	case DRM_FORMAT_P010:
2470 	case DRM_FORMAT_P012:
2471 	case DRM_FORMAT_P016:
2472 		if (intel_fb_is_mc_ccs_modifier(modifier))
2473 			return true;
2474 		fallthrough;
2475 	case DRM_FORMAT_RGB565:
2476 	case DRM_FORMAT_XVYU2101010:
2477 	case DRM_FORMAT_C8:
2478 	case DRM_FORMAT_Y210:
2479 	case DRM_FORMAT_Y212:
2480 	case DRM_FORMAT_Y216:
2481 	case DRM_FORMAT_XVYU12_16161616:
2482 	case DRM_FORMAT_XVYU16161616:
2483 		if (!intel_fb_is_ccs_modifier(modifier))
2484 			return true;
2485 		fallthrough;
2486 	default:
2487 		return false;
2488 	}
2489 }
2490 
2491 static const struct drm_plane_funcs skl_plane_funcs = {
2492 	.update_plane = drm_atomic_helper_update_plane,
2493 	.disable_plane = drm_atomic_helper_disable_plane,
2494 	.destroy = intel_plane_destroy,
2495 	.atomic_duplicate_state = intel_plane_duplicate_state,
2496 	.atomic_destroy_state = intel_plane_destroy_state,
2497 	.format_mod_supported = skl_plane_format_mod_supported,
2498 };
2499 
2500 static const struct drm_plane_funcs icl_plane_funcs = {
2501 	.update_plane = drm_atomic_helper_update_plane,
2502 	.disable_plane = drm_atomic_helper_disable_plane,
2503 	.destroy = intel_plane_destroy,
2504 	.atomic_duplicate_state = intel_plane_duplicate_state,
2505 	.atomic_destroy_state = intel_plane_destroy_state,
2506 	.format_mod_supported = icl_plane_format_mod_supported,
2507 };
2508 
2509 static const struct drm_plane_funcs tgl_plane_funcs = {
2510 	.update_plane = drm_atomic_helper_update_plane,
2511 	.disable_plane = drm_atomic_helper_disable_plane,
2512 	.destroy = intel_plane_destroy,
2513 	.atomic_duplicate_state = intel_plane_duplicate_state,
2514 	.atomic_destroy_state = intel_plane_destroy_state,
2515 	.format_mod_supported = tgl_plane_format_mod_supported,
2516 };
2517 
2518 static void
2519 skl_plane_enable_flip_done(struct intel_plane *plane)
2520 {
2521 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
2522 	enum pipe pipe = plane->pipe;
2523 
2524 	spin_lock_irq(&i915->irq_lock);
2525 	bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2526 	spin_unlock_irq(&i915->irq_lock);
2527 }
2528 
2529 static void
2530 skl_plane_disable_flip_done(struct intel_plane *plane)
2531 {
2532 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
2533 	enum pipe pipe = plane->pipe;
2534 
2535 	spin_lock_irq(&i915->irq_lock);
2536 	bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2537 	spin_unlock_irq(&i915->irq_lock);
2538 }
2539 
2540 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
2541 				 enum pipe pipe, enum plane_id plane_id)
2542 {
2543 	/* Wa_22011186057 */
2544 	if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2545 		return false;
2546 
2547 	if (DISPLAY_VER(i915) >= 11)
2548 		return true;
2549 
2550 	if (IS_GEMINILAKE(i915))
2551 		return pipe != PIPE_C;
2552 
2553 	return pipe != PIPE_C &&
2554 		(plane_id == PLANE_1 || plane_id == PLANE_2);
2555 }
2556 
2557 static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915,
2558 				 enum plane_id plane_id)
2559 {
2560 	if (DISPLAY_VER(i915) < 12)
2561 		return false;
2562 
2563 	/* Wa_14010477008 */
2564 	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
2565 		(IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
2566 		return false;
2567 
2568 	/* Wa_22011186057 */
2569 	if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2570 		return false;
2571 
2572 	return plane_id < PLANE_6;
2573 }
2574 
2575 static u8 skl_get_plane_caps(struct drm_i915_private *i915,
2576 			     enum pipe pipe, enum plane_id plane_id)
2577 {
2578 	struct intel_display *display = &i915->display;
2579 	u8 caps = INTEL_PLANE_CAP_TILING_X;
2580 
2581 	if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p)
2582 		caps |= INTEL_PLANE_CAP_TILING_Y;
2583 	if (DISPLAY_VER(display) < 12)
2584 		caps |= INTEL_PLANE_CAP_TILING_Yf;
2585 	if (HAS_4TILE(display))
2586 		caps |= INTEL_PLANE_CAP_TILING_4;
2587 
2588 	if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915))
2589 		return caps;
2590 
2591 	if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
2592 		caps |= INTEL_PLANE_CAP_CCS_RC;
2593 		if (DISPLAY_VER(display) >= 12)
2594 			caps |= INTEL_PLANE_CAP_CCS_RC_CC;
2595 	}
2596 
2597 	if (tgl_plane_has_mc_ccs(i915, plane_id))
2598 		caps |= INTEL_PLANE_CAP_CCS_MC;
2599 
2600 	if (DISPLAY_VER(display) >= 14 && display->platform.dgfx)
2601 		caps |= INTEL_PLANE_CAP_NEED64K_PHYS;
2602 
2603 	return caps;
2604 }
2605 
2606 struct intel_plane *
2607 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2608 			   enum pipe pipe, enum plane_id plane_id)
2609 {
2610 	const struct drm_plane_funcs *plane_funcs;
2611 	struct intel_plane *plane;
2612 	enum drm_plane_type plane_type;
2613 	unsigned int supported_rotations;
2614 	unsigned int supported_csc;
2615 	const u64 *modifiers;
2616 	const u32 *formats;
2617 	int num_formats;
2618 	int ret;
2619 
2620 	plane = intel_plane_alloc();
2621 	if (IS_ERR(plane))
2622 		return plane;
2623 
2624 	plane->pipe = pipe;
2625 	plane->id = plane_id;
2626 	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2627 
2628 	intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
2629 
2630 	if (DISPLAY_VER(dev_priv) >= 30) {
2631 		plane->max_width = xe3_plane_max_width;
2632 		plane->max_height = icl_plane_max_height;
2633 		plane->min_cdclk = icl_plane_min_cdclk;
2634 	} else if (DISPLAY_VER(dev_priv) >= 11) {
2635 		plane->min_width = icl_plane_min_width;
2636 		if (icl_is_hdr_plane(dev_priv, plane_id))
2637 			plane->max_width = icl_hdr_plane_max_width;
2638 		else
2639 			plane->max_width = icl_sdr_plane_max_width;
2640 		plane->max_height = icl_plane_max_height;
2641 		plane->min_cdclk = icl_plane_min_cdclk;
2642 	} else if (DISPLAY_VER(dev_priv) >= 10) {
2643 		plane->max_width = glk_plane_max_width;
2644 		plane->max_height = skl_plane_max_height;
2645 		plane->min_cdclk = glk_plane_min_cdclk;
2646 	} else {
2647 		plane->max_width = skl_plane_max_width;
2648 		plane->max_height = skl_plane_max_height;
2649 		plane->min_cdclk = skl_plane_min_cdclk;
2650 	}
2651 
2652 	if (DISPLAY_VER(dev_priv) >= 13)
2653 		plane->max_stride = adl_plane_max_stride;
2654 	else
2655 		plane->max_stride = skl_plane_max_stride;
2656 
2657 	if (DISPLAY_VER(dev_priv) >= 12)
2658 		plane->min_alignment = tgl_plane_min_alignment;
2659 	else
2660 		plane->min_alignment = skl_plane_min_alignment;
2661 
2662 	if (DISPLAY_VER(dev_priv) >= 11) {
2663 		plane->update_noarm = icl_plane_update_noarm;
2664 		plane->update_arm = icl_plane_update_arm;
2665 		plane->disable_arm = icl_plane_disable_arm;
2666 	} else {
2667 		plane->update_noarm = skl_plane_update_noarm;
2668 		plane->update_arm = skl_plane_update_arm;
2669 		plane->disable_arm = skl_plane_disable_arm;
2670 	}
2671 	plane->get_hw_state = skl_plane_get_hw_state;
2672 	plane->check_plane = skl_plane_check;
2673 
2674 	if (plane_id == PLANE_1) {
2675 		plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10);
2676 		plane->async_flip = skl_plane_async_flip;
2677 		plane->enable_flip_done = skl_plane_enable_flip_done;
2678 		plane->disable_flip_done = skl_plane_disable_flip_done;
2679 	}
2680 
2681 	if (DISPLAY_VER(dev_priv) >= 11)
2682 		formats = icl_get_plane_formats(dev_priv, pipe,
2683 						plane_id, &num_formats);
2684 	else if (DISPLAY_VER(dev_priv) >= 10)
2685 		formats = glk_get_plane_formats(dev_priv, pipe,
2686 						plane_id, &num_formats);
2687 	else
2688 		formats = skl_get_plane_formats(dev_priv, pipe,
2689 						plane_id, &num_formats);
2690 
2691 	if (DISPLAY_VER(dev_priv) >= 12)
2692 		plane_funcs = &tgl_plane_funcs;
2693 	else if (DISPLAY_VER(dev_priv) == 11)
2694 		plane_funcs = &icl_plane_funcs;
2695 	else
2696 		plane_funcs = &skl_plane_funcs;
2697 
2698 	if (plane_id == PLANE_1)
2699 		plane_type = DRM_PLANE_TYPE_PRIMARY;
2700 	else
2701 		plane_type = DRM_PLANE_TYPE_OVERLAY;
2702 
2703 	modifiers = intel_fb_plane_get_modifiers(dev_priv,
2704 						 skl_get_plane_caps(dev_priv, pipe, plane_id));
2705 
2706 	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2707 				       0, plane_funcs,
2708 				       formats, num_formats, modifiers,
2709 				       plane_type,
2710 				       "plane %d%c", plane_id + 1,
2711 				       pipe_name(pipe));
2712 
2713 	kfree(modifiers);
2714 
2715 	if (ret)
2716 		goto fail;
2717 
2718 	if (DISPLAY_VER(dev_priv) >= 13)
2719 		supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2720 	else
2721 		supported_rotations =
2722 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2723 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2724 
2725 	if (DISPLAY_VER(dev_priv) >= 11)
2726 		supported_rotations |= DRM_MODE_REFLECT_X;
2727 
2728 	drm_plane_create_rotation_property(&plane->base,
2729 					   DRM_MODE_ROTATE_0,
2730 					   supported_rotations);
2731 
2732 	supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
2733 
2734 	if (DISPLAY_VER(dev_priv) >= 10)
2735 		supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
2736 
2737 	drm_plane_create_color_properties(&plane->base,
2738 					  supported_csc,
2739 					  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2740 					  BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2741 					  DRM_COLOR_YCBCR_BT709,
2742 					  DRM_COLOR_YCBCR_LIMITED_RANGE);
2743 
2744 	drm_plane_create_alpha_property(&plane->base);
2745 	drm_plane_create_blend_mode_property(&plane->base,
2746 					     BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2747 					     BIT(DRM_MODE_BLEND_PREMULTI) |
2748 					     BIT(DRM_MODE_BLEND_COVERAGE));
2749 
2750 	drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2751 
2752 	if (DISPLAY_VER(dev_priv) >= 12)
2753 		drm_plane_enable_fb_damage_clips(&plane->base);
2754 
2755 	if (DISPLAY_VER(dev_priv) >= 11)
2756 		drm_plane_create_scaling_filter_property(&plane->base,
2757 						BIT(DRM_SCALING_FILTER_DEFAULT) |
2758 						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
2759 
2760 	intel_plane_helper_add(plane);
2761 
2762 	return plane;
2763 
2764 fail:
2765 	intel_plane_free(plane);
2766 
2767 	return ERR_PTR(ret);
2768 }
2769 
2770 void
2771 skl_get_initial_plane_config(struct intel_crtc *crtc,
2772 			     struct intel_initial_plane_config *plane_config)
2773 {
2774 	struct intel_display *display = to_intel_display(crtc);
2775 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
2776 	struct drm_device *dev = crtc->base.dev;
2777 	struct drm_i915_private *dev_priv = to_i915(dev);
2778 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2779 	enum plane_id plane_id = plane->id;
2780 	enum pipe pipe;
2781 	u32 val, base, offset, stride_mult, tiling, alpha;
2782 	int fourcc, pixel_format;
2783 	unsigned int aligned_height;
2784 	struct drm_framebuffer *fb;
2785 	struct intel_framebuffer *intel_fb;
2786 	static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
2787 
2788 	if (!plane->get_hw_state(plane, &pipe))
2789 		return;
2790 
2791 	drm_WARN_ON(dev, pipe != crtc->pipe);
2792 
2793 	if (crtc_state->joiner_pipes) {
2794 		drm_dbg_kms(&dev_priv->drm,
2795 			    "Unsupported joiner configuration for initial FB\n");
2796 		return;
2797 	}
2798 
2799 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2800 	if (!intel_fb) {
2801 		drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
2802 		return;
2803 	}
2804 
2805 	fb = &intel_fb->base;
2806 
2807 	fb->dev = dev;
2808 
2809 	val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
2810 
2811 	if (DISPLAY_VER(dev_priv) >= 11)
2812 		pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
2813 	else
2814 		pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
2815 
2816 	if (DISPLAY_VER(dev_priv) >= 10) {
2817 		u32 color_ctl;
2818 
2819 		color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
2820 		alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
2821 	} else {
2822 		alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
2823 	}
2824 
2825 	fourcc = skl_format_to_fourcc(pixel_format,
2826 				      val & PLANE_CTL_ORDER_RGBX, alpha);
2827 	fb->format = drm_format_info(fourcc);
2828 
2829 	tiling = val & PLANE_CTL_TILED_MASK;
2830 	switch (tiling) {
2831 	case PLANE_CTL_TILED_LINEAR:
2832 		fb->modifier = DRM_FORMAT_MOD_LINEAR;
2833 		break;
2834 	case PLANE_CTL_TILED_X:
2835 		plane_config->tiling = I915_TILING_X;
2836 		fb->modifier = I915_FORMAT_MOD_X_TILED;
2837 		break;
2838 	case PLANE_CTL_TILED_Y:
2839 		plane_config->tiling = I915_TILING_Y;
2840 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2841 			if (DISPLAY_VER(dev_priv) >= 14)
2842 				fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
2843 			else if (DISPLAY_VER(dev_priv) >= 12)
2844 				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
2845 			else
2846 				fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
2847 		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2848 			if (DISPLAY_VER(dev_priv) >= 14)
2849 				fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
2850 			else
2851 				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2852 		else
2853 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
2854 		break;
2855 	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
2856 		if (HAS_4TILE(display)) {
2857 			u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
2858 				      PLANE_CTL_CLEAR_COLOR_DISABLE;
2859 
2860 			if ((val & rc_mask) == rc_mask)
2861 				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
2862 			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2863 				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
2864 			else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2865 				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
2866 			else
2867 				fb->modifier = I915_FORMAT_MOD_4_TILED;
2868 		} else {
2869 			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2870 				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
2871 			else
2872 				fb->modifier = I915_FORMAT_MOD_Yf_TILED;
2873 		}
2874 		break;
2875 	default:
2876 		MISSING_CASE(tiling);
2877 		goto error;
2878 	}
2879 
2880 	if (!dev_priv->display.params.enable_dpt &&
2881 	    intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
2882 		drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n");
2883 		goto error;
2884 	}
2885 
2886 	/*
2887 	 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
2888 	 * while i915 HW rotation is clockwise, thats why this swapping.
2889 	 */
2890 	switch (val & PLANE_CTL_ROTATE_MASK) {
2891 	case PLANE_CTL_ROTATE_0:
2892 		plane_config->rotation = DRM_MODE_ROTATE_0;
2893 		break;
2894 	case PLANE_CTL_ROTATE_90:
2895 		plane_config->rotation = DRM_MODE_ROTATE_270;
2896 		break;
2897 	case PLANE_CTL_ROTATE_180:
2898 		plane_config->rotation = DRM_MODE_ROTATE_180;
2899 		break;
2900 	case PLANE_CTL_ROTATE_270:
2901 		plane_config->rotation = DRM_MODE_ROTATE_90;
2902 		break;
2903 	}
2904 
2905 	if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
2906 		plane_config->rotation |= DRM_MODE_REFLECT_X;
2907 
2908 	/* 90/270 degree rotation would require extra work */
2909 	if (drm_rotation_90_or_270(plane_config->rotation))
2910 		goto error;
2911 
2912 	base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
2913 	plane_config->base = base;
2914 
2915 	offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
2916 	drm_WARN_ON(&dev_priv->drm, offset != 0);
2917 
2918 	val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2919 	fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
2920 	fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
2921 
2922 	val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
2923 	stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
2924 
2925 	fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
2926 
2927 	aligned_height = intel_fb_align_height(fb, 0, fb->height);
2928 
2929 	plane_config->size = fb->pitches[0] * aligned_height;
2930 
2931 	drm_dbg_kms(&dev_priv->drm,
2932 		    "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
2933 		    crtc->base.name, plane->base.name, fb->width, fb->height,
2934 		    fb->format->cpp[0] * 8, base, fb->pitches[0],
2935 		    plane_config->size);
2936 
2937 	plane_config->fb = intel_fb;
2938 	return;
2939 
2940 error:
2941 	kfree(intel_fb);
2942 }
2943 
2944 bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
2945 				    const struct intel_initial_plane_config *plane_config)
2946 {
2947 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2948 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2949 	const struct intel_plane_state *plane_state =
2950 		to_intel_plane_state(plane->base.state);
2951 	enum plane_id plane_id = plane->id;
2952 	enum pipe pipe = crtc->pipe;
2953 	u32 base;
2954 
2955 	if (!plane_state->uapi.visible)
2956 		return false;
2957 
2958 	base = intel_plane_ggtt_offset(plane_state);
2959 
2960 	/*
2961 	 * We may have moved the surface to a different
2962 	 * part of ggtt, make the plane aware of that.
2963 	 */
2964 	if (plane_config->base == base)
2965 		return false;
2966 
2967 	intel_de_write(i915, PLANE_SURF(pipe, plane_id), base);
2968 
2969 	return true;
2970 }
2971