1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/mlx4/qp.h> 36 #include <linux/mlx4/srq.h> 37 #include <linux/slab.h> 38 39 #include "mlx4_ib.h" 40 #include <rdma/mlx4-abi.h> 41 #include <rdma/uverbs_ioctl.h> 42 43 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 44 { 45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 46 ibcq->comp_handler(ibcq, ibcq->cq_context); 47 } 48 49 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 50 { 51 struct ib_event event; 52 struct ib_cq *ibcq; 53 54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 55 pr_warn("Unexpected event type %d " 56 "on CQ %06x\n", type, cq->cqn); 57 return; 58 } 59 60 ibcq = &to_mibcq(cq)->ibcq; 61 if (ibcq->event_handler) { 62 event.device = ibcq->device; 63 event.event = IB_EVENT_CQ_ERR; 64 event.element.cq = ibcq; 65 ibcq->event_handler(&event, ibcq->cq_context); 66 } 67 } 68 69 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 70 { 71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 72 } 73 74 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 75 { 76 return get_cqe_from_buf(&cq->buf, n); 77 } 78 79 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 80 { 81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 83 84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 86 } 87 88 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 89 { 90 return get_sw_cqe(cq, cq->mcq.cons_index); 91 } 92 93 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 94 { 95 struct mlx4_ib_cq *mcq = to_mcq(cq); 96 struct mlx4_ib_dev *dev = to_mdev(cq->device); 97 98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 99 } 100 101 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 102 { 103 int err; 104 105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 106 PAGE_SIZE * 2, &buf->buf); 107 108 if (err) 109 goto out; 110 111 buf->entry_size = dev->dev->caps.cqe_size; 112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 113 &buf->mtt); 114 if (err) 115 goto err_buf; 116 117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); 118 if (err) 119 goto err_mtt; 120 121 return 0; 122 123 err_mtt: 124 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 125 126 err_buf: 127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 128 129 out: 130 return err; 131 } 132 133 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 134 { 135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 136 } 137 138 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, 139 struct mlx4_ib_cq_buf *buf, 140 struct ib_umem **umem, u64 buf_addr, int cqe) 141 { 142 int err; 143 int cqe_size = dev->dev->caps.cqe_size; 144 int shift; 145 int n; 146 147 *umem = ib_umem_get(&dev->ib_dev, buf_addr, cqe * cqe_size, 148 IB_ACCESS_LOCAL_WRITE); 149 if (IS_ERR(*umem)) 150 return PTR_ERR(*umem); 151 152 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n); 153 if (shift < 0) { 154 err = shift; 155 goto err_buf; 156 } 157 158 err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt); 159 if (err) 160 goto err_buf; 161 162 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 163 if (err) 164 goto err_mtt; 165 166 return 0; 167 168 err_mtt: 169 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 170 171 err_buf: 172 ib_umem_release(*umem); 173 174 return err; 175 } 176 177 #define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION 178 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 179 struct uverbs_attr_bundle *attrs) 180 { 181 struct ib_udata *udata = &attrs->driver_udata; 182 struct ib_device *ibdev = ibcq->device; 183 int entries = attr->cqe; 184 int vector = attr->comp_vector; 185 struct mlx4_ib_dev *dev = to_mdev(ibdev); 186 struct mlx4_ib_cq *cq = to_mcq(ibcq); 187 struct mlx4_uar *uar; 188 void *buf_addr; 189 int err; 190 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 191 udata, struct mlx4_ib_ucontext, ibucontext); 192 193 if (entries < 1 || entries > dev->dev->caps.max_cqes) 194 return -EINVAL; 195 196 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 197 return -EINVAL; 198 199 entries = roundup_pow_of_two(entries + 1); 200 cq->ibcq.cqe = entries - 1; 201 mutex_init(&cq->resize_mutex); 202 spin_lock_init(&cq->lock); 203 cq->resize_buf = NULL; 204 cq->resize_umem = NULL; 205 cq->create_flags = attr->flags; 206 INIT_LIST_HEAD(&cq->send_qp_list); 207 INIT_LIST_HEAD(&cq->recv_qp_list); 208 209 if (udata) { 210 struct mlx4_ib_create_cq ucmd; 211 212 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 213 err = -EFAULT; 214 goto err_cq; 215 } 216 217 buf_addr = (void *)(unsigned long)ucmd.buf_addr; 218 err = mlx4_ib_get_cq_umem(dev, &cq->buf, &cq->umem, 219 ucmd.buf_addr, entries); 220 if (err) 221 goto err_cq; 222 223 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &cq->db); 224 if (err) 225 goto err_mtt; 226 227 uar = &context->uar; 228 cq->mcq.usage = MLX4_RES_USAGE_USER_VERBS; 229 } else { 230 err = mlx4_db_alloc(dev->dev, &cq->db, 1); 231 if (err) 232 goto err_cq; 233 234 cq->mcq.set_ci_db = cq->db.db; 235 cq->mcq.arm_db = cq->db.db + 1; 236 *cq->mcq.set_ci_db = 0; 237 *cq->mcq.arm_db = 0; 238 239 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 240 if (err) 241 goto err_db; 242 243 buf_addr = &cq->buf.buf; 244 245 uar = &dev->priv_uar; 246 cq->mcq.usage = MLX4_RES_USAGE_DRIVER; 247 } 248 249 if (dev->eq_table) 250 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 251 252 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, cq->db.dma, 253 &cq->mcq, vector, 0, 254 !!(cq->create_flags & 255 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION), 256 buf_addr, !!udata); 257 if (err) 258 goto err_dbmap; 259 260 if (udata) 261 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp; 262 else 263 cq->mcq.comp = mlx4_ib_cq_comp; 264 cq->mcq.event = mlx4_ib_cq_event; 265 266 if (udata) 267 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 268 err = -EFAULT; 269 goto err_cq_free; 270 } 271 272 return 0; 273 274 err_cq_free: 275 mlx4_cq_free(dev->dev, &cq->mcq); 276 277 err_dbmap: 278 if (udata) 279 mlx4_ib_db_unmap_user(context, &cq->db); 280 281 err_mtt: 282 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 283 284 ib_umem_release(cq->umem); 285 if (!udata) 286 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 287 288 err_db: 289 if (!udata) 290 mlx4_db_free(dev->dev, &cq->db); 291 err_cq: 292 return err; 293 } 294 295 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 296 int entries) 297 { 298 int err; 299 300 if (cq->resize_buf) 301 return -EBUSY; 302 303 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 304 if (!cq->resize_buf) 305 return -ENOMEM; 306 307 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 308 if (err) { 309 kfree(cq->resize_buf); 310 cq->resize_buf = NULL; 311 return err; 312 } 313 314 cq->resize_buf->cqe = entries - 1; 315 316 return 0; 317 } 318 319 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 320 int entries, struct ib_udata *udata) 321 { 322 struct mlx4_ib_resize_cq ucmd; 323 int err; 324 325 if (cq->resize_umem) 326 return -EBUSY; 327 328 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 329 return -EFAULT; 330 331 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 332 if (!cq->resize_buf) 333 return -ENOMEM; 334 335 err = mlx4_ib_get_cq_umem(dev, &cq->resize_buf->buf, &cq->resize_umem, 336 ucmd.buf_addr, entries); 337 if (err) { 338 kfree(cq->resize_buf); 339 cq->resize_buf = NULL; 340 return err; 341 } 342 343 cq->resize_buf->cqe = entries - 1; 344 345 return 0; 346 } 347 348 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 349 { 350 u32 i; 351 352 i = cq->mcq.cons_index; 353 while (get_sw_cqe(cq, i)) 354 ++i; 355 356 return i - cq->mcq.cons_index; 357 } 358 359 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 360 { 361 struct mlx4_cqe *cqe, *new_cqe; 362 int i; 363 int cqe_size = cq->buf.entry_size; 364 int cqe_inc = cqe_size == 64 ? 1 : 0; 365 366 i = cq->mcq.cons_index; 367 cqe = get_cqe(cq, i & cq->ibcq.cqe); 368 cqe += cqe_inc; 369 370 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 371 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 372 (i + 1) & cq->resize_buf->cqe); 373 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 374 new_cqe += cqe_inc; 375 376 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 377 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 378 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 379 cqe += cqe_inc; 380 } 381 ++cq->mcq.cons_index; 382 } 383 384 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 385 { 386 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 387 struct mlx4_ib_cq *cq = to_mcq(ibcq); 388 struct mlx4_mtt mtt; 389 int outst_cqe; 390 int err; 391 392 mutex_lock(&cq->resize_mutex); 393 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 394 err = -EINVAL; 395 goto out; 396 } 397 398 entries = roundup_pow_of_two(entries + 1); 399 if (entries == ibcq->cqe + 1) { 400 err = 0; 401 goto out; 402 } 403 404 if (entries > dev->dev->caps.max_cqes + 1) { 405 err = -EINVAL; 406 goto out; 407 } 408 409 if (ibcq->uobject) { 410 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 411 if (err) 412 goto out; 413 } else { 414 /* Can't be smaller than the number of outstanding CQEs */ 415 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 416 if (entries < outst_cqe + 1) { 417 err = -EINVAL; 418 goto out; 419 } 420 421 err = mlx4_alloc_resize_buf(dev, cq, entries); 422 if (err) 423 goto out; 424 } 425 426 mtt = cq->buf.mtt; 427 428 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 429 if (err) 430 goto err_buf; 431 432 mlx4_mtt_cleanup(dev->dev, &mtt); 433 if (ibcq->uobject) { 434 cq->buf = cq->resize_buf->buf; 435 cq->ibcq.cqe = cq->resize_buf->cqe; 436 ib_umem_release(cq->umem); 437 cq->umem = cq->resize_umem; 438 439 kfree(cq->resize_buf); 440 cq->resize_buf = NULL; 441 cq->resize_umem = NULL; 442 } else { 443 struct mlx4_ib_cq_buf tmp_buf; 444 int tmp_cqe = 0; 445 446 spin_lock_irq(&cq->lock); 447 if (cq->resize_buf) { 448 mlx4_ib_cq_resize_copy_cqes(cq); 449 tmp_buf = cq->buf; 450 tmp_cqe = cq->ibcq.cqe; 451 cq->buf = cq->resize_buf->buf; 452 cq->ibcq.cqe = cq->resize_buf->cqe; 453 454 kfree(cq->resize_buf); 455 cq->resize_buf = NULL; 456 } 457 spin_unlock_irq(&cq->lock); 458 459 if (tmp_cqe) 460 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 461 } 462 463 goto out; 464 465 err_buf: 466 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 467 if (!ibcq->uobject) 468 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 469 cq->resize_buf->cqe); 470 471 kfree(cq->resize_buf); 472 cq->resize_buf = NULL; 473 474 ib_umem_release(cq->resize_umem); 475 cq->resize_umem = NULL; 476 out: 477 mutex_unlock(&cq->resize_mutex); 478 479 return err; 480 } 481 482 int mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 483 { 484 struct mlx4_ib_dev *dev = to_mdev(cq->device); 485 struct mlx4_ib_cq *mcq = to_mcq(cq); 486 487 mlx4_cq_free(dev->dev, &mcq->mcq); 488 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 489 490 if (udata) { 491 mlx4_ib_db_unmap_user( 492 rdma_udata_to_drv_context( 493 udata, 494 struct mlx4_ib_ucontext, 495 ibucontext), 496 &mcq->db); 497 } else { 498 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 499 mlx4_db_free(dev->dev, &mcq->db); 500 } 501 ib_umem_release(mcq->umem); 502 return 0; 503 } 504 505 static void dump_cqe(void *cqe) 506 { 507 __be32 *buf = cqe; 508 509 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 510 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 511 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 512 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 513 } 514 515 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 516 struct ib_wc *wc) 517 { 518 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 519 pr_debug("local QP operation err " 520 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 521 "opcode = %02x)\n", 522 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 523 cqe->vendor_err_syndrome, 524 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 525 dump_cqe(cqe); 526 } 527 528 switch (cqe->syndrome) { 529 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 530 wc->status = IB_WC_LOC_LEN_ERR; 531 break; 532 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 533 wc->status = IB_WC_LOC_QP_OP_ERR; 534 break; 535 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 536 wc->status = IB_WC_LOC_PROT_ERR; 537 break; 538 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 539 wc->status = IB_WC_WR_FLUSH_ERR; 540 break; 541 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 542 wc->status = IB_WC_MW_BIND_ERR; 543 break; 544 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 545 wc->status = IB_WC_BAD_RESP_ERR; 546 break; 547 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 548 wc->status = IB_WC_LOC_ACCESS_ERR; 549 break; 550 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 551 wc->status = IB_WC_REM_INV_REQ_ERR; 552 break; 553 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 554 wc->status = IB_WC_REM_ACCESS_ERR; 555 break; 556 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 557 wc->status = IB_WC_REM_OP_ERR; 558 break; 559 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 560 wc->status = IB_WC_RETRY_EXC_ERR; 561 break; 562 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 563 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 564 break; 565 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 566 wc->status = IB_WC_REM_ABORT_ERR; 567 break; 568 default: 569 wc->status = IB_WC_GENERAL_ERR; 570 break; 571 } 572 573 wc->vendor_err = cqe->vendor_err_syndrome; 574 } 575 576 static int mlx4_ib_ipoib_csum_ok(__be16 status, u8 badfcs_enc, __be16 checksum) 577 { 578 return ((badfcs_enc & MLX4_CQE_STATUS_L4_CSUM) || 579 ((status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 580 (status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 581 MLX4_CQE_STATUS_UDP)) && 582 (checksum == cpu_to_be16(0xffff)))); 583 } 584 585 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 586 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 587 { 588 struct mlx4_ib_proxy_sqp_hdr *hdr; 589 590 ib_dma_sync_single_for_cpu(qp->ibqp.device, 591 qp->sqp_proxy_rcv[tail].map, 592 sizeof (struct mlx4_ib_proxy_sqp_hdr), 593 DMA_FROM_DEVICE); 594 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 595 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 596 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 597 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 598 wc->dlid_path_bits = 0; 599 600 if (is_eth) { 601 wc->slid = 0; 602 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 603 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 604 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 605 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 606 } else { 607 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 608 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 609 } 610 } 611 612 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 613 struct ib_wc *wc, int *npolled, int is_send) 614 { 615 struct mlx4_ib_wq *wq; 616 unsigned cur; 617 int i; 618 619 wq = is_send ? &qp->sq : &qp->rq; 620 cur = wq->head - wq->tail; 621 622 if (cur == 0) 623 return; 624 625 for (i = 0; i < cur && *npolled < num_entries; i++) { 626 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 627 wc->status = IB_WC_WR_FLUSH_ERR; 628 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 629 wq->tail++; 630 (*npolled)++; 631 wc->qp = &qp->ibqp; 632 wc++; 633 } 634 } 635 636 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 637 struct ib_wc *wc, int *npolled) 638 { 639 struct mlx4_ib_qp *qp; 640 641 *npolled = 0; 642 /* Find uncompleted WQEs belonging to that cq and return 643 * simulated FLUSH_ERR completions 644 */ 645 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 646 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 647 if (*npolled >= num_entries) 648 goto out; 649 } 650 651 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 652 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 653 if (*npolled >= num_entries) 654 goto out; 655 } 656 657 out: 658 return; 659 } 660 661 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 662 struct mlx4_ib_qp **cur_qp, 663 struct ib_wc *wc) 664 { 665 struct mlx4_cqe *cqe; 666 struct mlx4_qp *mqp; 667 struct mlx4_ib_wq *wq; 668 struct mlx4_ib_srq *srq; 669 struct mlx4_srq *msrq = NULL; 670 int is_send; 671 int is_error; 672 int is_eth; 673 u32 g_mlpath_rqpn; 674 u16 wqe_ctr; 675 unsigned tail = 0; 676 677 repoll: 678 cqe = next_cqe_sw(cq); 679 if (!cqe) 680 return -EAGAIN; 681 682 if (cq->buf.entry_size == 64) 683 cqe++; 684 685 ++cq->mcq.cons_index; 686 687 /* 688 * Make sure we read CQ entry contents after we've checked the 689 * ownership bit. 690 */ 691 rmb(); 692 693 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 694 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 695 MLX4_CQE_OPCODE_ERROR; 696 697 /* Resize CQ in progress */ 698 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 699 if (cq->resize_buf) { 700 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 701 702 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 703 cq->buf = cq->resize_buf->buf; 704 cq->ibcq.cqe = cq->resize_buf->cqe; 705 706 kfree(cq->resize_buf); 707 cq->resize_buf = NULL; 708 } 709 710 goto repoll; 711 } 712 713 if (!*cur_qp || 714 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 715 /* 716 * We do not have to take the QP table lock here, 717 * because CQs will be locked while QPs are removed 718 * from the table. 719 */ 720 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 721 be32_to_cpu(cqe->vlan_my_qpn)); 722 *cur_qp = to_mibqp(mqp); 723 } 724 725 wc->qp = &(*cur_qp)->ibqp; 726 727 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 728 u32 srq_num; 729 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 730 srq_num = g_mlpath_rqpn & 0xffffff; 731 /* SRQ is also in the radix tree */ 732 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 733 srq_num); 734 } 735 736 if (is_send) { 737 wq = &(*cur_qp)->sq; 738 if (!(*cur_qp)->sq_signal_bits) { 739 wqe_ctr = be16_to_cpu(cqe->wqe_index); 740 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 741 } 742 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 743 ++wq->tail; 744 } else if ((*cur_qp)->ibqp.srq) { 745 srq = to_msrq((*cur_qp)->ibqp.srq); 746 wqe_ctr = be16_to_cpu(cqe->wqe_index); 747 wc->wr_id = srq->wrid[wqe_ctr]; 748 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 749 } else if (msrq) { 750 srq = to_mibsrq(msrq); 751 wqe_ctr = be16_to_cpu(cqe->wqe_index); 752 wc->wr_id = srq->wrid[wqe_ctr]; 753 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 754 } else { 755 wq = &(*cur_qp)->rq; 756 tail = wq->tail & (wq->wqe_cnt - 1); 757 wc->wr_id = wq->wrid[tail]; 758 ++wq->tail; 759 } 760 761 if (unlikely(is_error)) { 762 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 763 return 0; 764 } 765 766 wc->status = IB_WC_SUCCESS; 767 768 if (is_send) { 769 wc->wc_flags = 0; 770 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 771 case MLX4_OPCODE_RDMA_WRITE_IMM: 772 wc->wc_flags |= IB_WC_WITH_IMM; 773 fallthrough; 774 case MLX4_OPCODE_RDMA_WRITE: 775 wc->opcode = IB_WC_RDMA_WRITE; 776 break; 777 case MLX4_OPCODE_SEND_IMM: 778 wc->wc_flags |= IB_WC_WITH_IMM; 779 fallthrough; 780 case MLX4_OPCODE_SEND: 781 case MLX4_OPCODE_SEND_INVAL: 782 wc->opcode = IB_WC_SEND; 783 break; 784 case MLX4_OPCODE_RDMA_READ: 785 wc->opcode = IB_WC_RDMA_READ; 786 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 787 break; 788 case MLX4_OPCODE_ATOMIC_CS: 789 wc->opcode = IB_WC_COMP_SWAP; 790 wc->byte_len = 8; 791 break; 792 case MLX4_OPCODE_ATOMIC_FA: 793 wc->opcode = IB_WC_FETCH_ADD; 794 wc->byte_len = 8; 795 break; 796 case MLX4_OPCODE_MASKED_ATOMIC_CS: 797 wc->opcode = IB_WC_MASKED_COMP_SWAP; 798 wc->byte_len = 8; 799 break; 800 case MLX4_OPCODE_MASKED_ATOMIC_FA: 801 wc->opcode = IB_WC_MASKED_FETCH_ADD; 802 wc->byte_len = 8; 803 break; 804 case MLX4_OPCODE_LSO: 805 wc->opcode = IB_WC_LSO; 806 break; 807 case MLX4_OPCODE_FMR: 808 wc->opcode = IB_WC_REG_MR; 809 break; 810 case MLX4_OPCODE_LOCAL_INVAL: 811 wc->opcode = IB_WC_LOCAL_INV; 812 break; 813 } 814 } else { 815 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 816 817 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 818 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 819 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 820 wc->wc_flags = IB_WC_WITH_IMM; 821 wc->ex.imm_data = cqe->immed_rss_invalid; 822 break; 823 case MLX4_RECV_OPCODE_SEND_INVAL: 824 wc->opcode = IB_WC_RECV; 825 wc->wc_flags = IB_WC_WITH_INVALIDATE; 826 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 827 break; 828 case MLX4_RECV_OPCODE_SEND: 829 wc->opcode = IB_WC_RECV; 830 wc->wc_flags = 0; 831 break; 832 case MLX4_RECV_OPCODE_SEND_IMM: 833 wc->opcode = IB_WC_RECV; 834 wc->wc_flags = IB_WC_WITH_IMM; 835 wc->ex.imm_data = cqe->immed_rss_invalid; 836 break; 837 } 838 839 is_eth = (rdma_port_get_link_layer(wc->qp->device, 840 (*cur_qp)->port) == 841 IB_LINK_LAYER_ETHERNET); 842 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 843 if ((*cur_qp)->mlx4_ib_qp_type & 844 (MLX4_IB_QPT_PROXY_SMI_OWNER | 845 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 846 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 847 is_eth); 848 return 0; 849 } 850 } 851 852 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 853 wc->src_qp = g_mlpath_rqpn & 0xffffff; 854 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 855 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 856 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 857 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 858 cqe->badfcs_enc, 859 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 860 if (is_eth) { 861 wc->slid = 0; 862 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 863 if (be32_to_cpu(cqe->vlan_my_qpn) & 864 MLX4_CQE_CVLAN_PRESENT_MASK) { 865 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 866 MLX4_CQE_VID_MASK; 867 } else { 868 wc->vlan_id = 0xffff; 869 } 870 memcpy(wc->smac, cqe->smac, ETH_ALEN); 871 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 872 } else { 873 wc->slid = be16_to_cpu(cqe->rlid); 874 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 875 wc->vlan_id = 0xffff; 876 } 877 } 878 879 return 0; 880 } 881 882 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 883 { 884 struct mlx4_ib_cq *cq = to_mcq(ibcq); 885 struct mlx4_ib_qp *cur_qp = NULL; 886 unsigned long flags; 887 int npolled; 888 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 889 890 spin_lock_irqsave(&cq->lock, flags); 891 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 892 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 893 goto out; 894 } 895 896 for (npolled = 0; npolled < num_entries; ++npolled) { 897 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 898 break; 899 } 900 901 mlx4_cq_set_ci(&cq->mcq); 902 903 out: 904 spin_unlock_irqrestore(&cq->lock, flags); 905 906 return npolled; 907 } 908 909 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 910 { 911 mlx4_cq_arm(&to_mcq(ibcq)->mcq, 912 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 913 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 914 to_mdev(ibcq->device)->uar_map, 915 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); 916 917 return 0; 918 } 919 920 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 921 { 922 u32 prod_index; 923 int nfreed = 0; 924 struct mlx4_cqe *cqe, *dest; 925 u8 owner_bit; 926 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 927 928 /* 929 * First we need to find the current producer index, so we 930 * know where to start cleaning from. It doesn't matter if HW 931 * adds new entries after this loop -- the QP we're worried 932 * about is already in RESET, so the new entries won't come 933 * from our QP and therefore don't need to be checked. 934 */ 935 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 936 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 937 break; 938 939 /* 940 * Now sweep backwards through the CQ, removing CQ entries 941 * that match our QP by copying older entries on top of them. 942 */ 943 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 944 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 945 cqe += cqe_inc; 946 947 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 948 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 949 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 950 ++nfreed; 951 } else if (nfreed) { 952 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 953 dest += cqe_inc; 954 955 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 956 memcpy(dest, cqe, sizeof *cqe); 957 dest->owner_sr_opcode = owner_bit | 958 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 959 } 960 } 961 962 if (nfreed) { 963 cq->mcq.cons_index += nfreed; 964 /* 965 * Make sure update of buffer contents is done before 966 * updating consumer index. 967 */ 968 wmb(); 969 mlx4_cq_set_ci(&cq->mcq); 970 } 971 } 972 973 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 974 { 975 spin_lock_irq(&cq->lock); 976 __mlx4_ib_cq_clean(cq, qpn, srq); 977 spin_unlock_irq(&cq->lock); 978 } 979