1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_PORT_H__ 8 #define __SPARX5_PORT_H__ 9 10 #include "sparx5_main.h" 11 12 /* Port PCP rewrite mode */ 13 #define SPARX5_PORT_REW_TAG_CTRL_CLASSIFIED 0 14 #define SPARX5_PORT_REW_TAG_CTRL_DEFAULT 1 15 #define SPARX5_PORT_REW_TAG_CTRL_MAPPED 2 16 17 /* Port DSCP rewrite mode */ 18 #define SPARX5_PORT_REW_DSCP_NONE 0 19 #define SPARX5_PORT_REW_DSCP_IF_ZERO 1 20 #define SPARX5_PORT_REW_DSCP_SELECTED 2 21 #define SPARX5_PORT_REW_DSCP_ALL 3 22 23 static inline bool sparx5_port_is_2g5(int portno) 24 { 25 return portno >= 16 && portno <= 47; 26 } 27 28 static inline bool sparx5_port_is_5g(int portno) 29 { 30 return portno <= 11 || portno == 64; 31 } 32 33 static inline bool sparx5_port_is_10g(int portno) 34 { 35 return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55); 36 } 37 38 static inline bool sparx5_port_is_25g(int portno) 39 { 40 return portno >= 56 && portno <= 63; 41 } 42 43 static inline bool sparx5_port_is_rgmii(int portno) 44 { 45 return false; 46 } 47 48 static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) 49 { 50 const struct sparx5_ops *ops = sparx5->data->ops; 51 52 if (ops->is_port_5g(port)) 53 return TARGET_DEV5G; 54 if (ops->is_port_10g(port)) 55 return TARGET_DEV10G; 56 return TARGET_DEV25G; 57 } 58 59 static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) 60 { 61 const struct sparx5_ops *ops = sparx5->data->ops; 62 63 if (ops->is_port_5g(port)) 64 return TARGET_PCS5G_BR; 65 if (ops->is_port_10g(port)) 66 return TARGET_PCS10G_BR; 67 return TARGET_PCS25G_BR; 68 } 69 70 static inline u32 sparx5_port_dev_mapping(struct sparx5 *sparx5, int port) 71 { 72 if (sparx5_port_is_2g5(port)) 73 return port; 74 if (sparx5_port_is_5g(port)) 75 return (port <= 11 ? port : 12); 76 if (sparx5_port_is_10g(port)) 77 return (port >= 12 && port <= 15) ? 78 port - 12 : port - 44; 79 return (port - 56); 80 } 81 82 static inline u32 sparx5_port_dev_index(struct sparx5 *sparx5, int port) 83 { 84 return sparx5->data->ops->get_port_dev_index(sparx5, port); 85 } 86 87 int sparx5_port_init(struct sparx5 *sparx5, 88 struct sparx5_port *spx5_port, 89 struct sparx5_port_config *conf); 90 91 int sparx5_port_config(struct sparx5 *sparx5, 92 struct sparx5_port *spx5_port, 93 struct sparx5_port_config *conf); 94 95 int sparx5_port_pcs_set(struct sparx5 *sparx5, 96 struct sparx5_port *port, 97 struct sparx5_port_config *conf); 98 99 int sparx5_serdes_set(struct sparx5 *sparx5, 100 struct sparx5_port *spx5_port, 101 struct sparx5_port_config *conf); 102 103 struct sparx5_port_status { 104 bool link; 105 bool link_down; 106 int speed; 107 bool an_complete; 108 int duplex; 109 int pause; 110 }; 111 112 int sparx5_get_port_status(struct sparx5 *sparx5, 113 struct sparx5_port *port, 114 struct sparx5_port_status *status); 115 116 void sparx5_port_enable(struct sparx5_port *port, bool enable); 117 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed); 118 119 #define SPARX5_PORT_QOS_PCP_COUNT 8 120 #define SPARX5_PORT_QOS_DEI_COUNT 8 121 #define SPARX5_PORT_QOS_PCP_DEI_COUNT \ 122 (SPARX5_PORT_QOS_PCP_COUNT + SPARX5_PORT_QOS_DEI_COUNT) 123 struct sparx5_port_qos_pcp_map { 124 u8 map[SPARX5_PORT_QOS_PCP_DEI_COUNT]; 125 }; 126 127 struct sparx5_port_qos_pcp_rewr_map { 128 u16 map[SPX5_PRIOS]; 129 }; 130 131 #define SPARX5_PORT_QOS_DP_NUM 4 132 struct sparx5_port_qos_dscp_rewr_map { 133 u16 map[SPX5_PRIOS * SPARX5_PORT_QOS_DP_NUM]; 134 }; 135 136 #define SPARX5_PORT_QOS_DSCP_COUNT 64 137 struct sparx5_port_qos_dscp_map { 138 u8 map[SPARX5_PORT_QOS_DSCP_COUNT]; 139 }; 140 141 struct sparx5_port_qos_pcp { 142 struct sparx5_port_qos_pcp_map map; 143 bool qos_enable; 144 bool dp_enable; 145 }; 146 147 struct sparx5_port_qos_pcp_rewr { 148 struct sparx5_port_qos_pcp_rewr_map map; 149 bool enable; 150 }; 151 152 struct sparx5_port_qos_dscp { 153 struct sparx5_port_qos_dscp_map map; 154 bool qos_enable; 155 bool dp_enable; 156 }; 157 158 struct sparx5_port_qos_dscp_rewr { 159 struct sparx5_port_qos_dscp_rewr_map map; 160 bool enable; 161 }; 162 163 struct sparx5_port_qos { 164 struct sparx5_port_qos_pcp pcp; 165 struct sparx5_port_qos_pcp_rewr pcp_rewr; 166 struct sparx5_port_qos_dscp dscp; 167 struct sparx5_port_qos_dscp_rewr dscp_rewr; 168 u8 default_prio; 169 }; 170 171 int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos); 172 173 int sparx5_port_qos_pcp_set(const struct sparx5_port *port, 174 struct sparx5_port_qos_pcp *qos); 175 176 int sparx5_port_qos_pcp_rewr_set(const struct sparx5_port *port, 177 struct sparx5_port_qos_pcp_rewr *qos); 178 179 int sparx5_port_qos_dscp_set(const struct sparx5_port *port, 180 struct sparx5_port_qos_dscp *qos); 181 182 void sparx5_port_qos_dscp_rewr_mode_set(const struct sparx5_port *port, 183 int mode); 184 185 int sparx5_port_qos_dscp_rewr_set(const struct sparx5_port *port, 186 struct sparx5_port_qos_dscp_rewr *qos); 187 188 int sparx5_port_qos_default_set(const struct sparx5_port *port, 189 const struct sparx5_port_qos *qos); 190 191 #endif /* __SPARX5_PORT_H__ */ 192