| 55593618 | 21-Oct-2024 |
Benjamin Gaignard <benjamin.gaignard@collabora.com> |
media: verisilicon: av1: Store chroma and mv offsets
Store the chroma and motion vector offsets for each frame so that they
can be used later when the resolution changes.
Signed-off-by: Benjamin Ga
media: verisilicon: av1: Store chroma and mv offsets
Store the chroma and motion vector offsets for each frame so that they
can be used later when the resolution changes.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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| e5453f2a | 12-Dec-2024 |
Benjamin Gaignard <benjamin.gaignard@collabora.com> |
media: verisilicon: Fix IMX8 native pixel-format step values
The Hantro decoder non post-processed pixel-format steps are different
from the post-processed ones. Fix the steps according to the hardw
media: verisilicon: Fix IMX8 native pixel-format step values
The Hantro decoder non post-processed pixel-format steps are different
from the post-processed ones. Fix the steps according to the hardware
limitations. Since reference frame pixel-format issues have been fixed,
it is possible to use V4L2_PIX_FMT_NV15_4L4 rather V4L2_PIX_FMT_P010_4L4
for 10bit streams.
Fluster VP9 score goes up to 207/305.
HEVC score is still 141/147.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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| 90effee4 | 18-Jun-2024 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
media: hantro: Add RK3588 VEPU121
RK3588 handling is exactly the same as RK3568. This is not
handled using fallback compatibles to avoid exposing multiple
video devices on kernels not having the mul
media: hantro: Add RK3588 VEPU121
RK3588 handling is exactly the same as RK3568. This is not
handled using fallback compatibles to avoid exposing multiple
video devices on kernels not having the multicore disable
patch.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| ccdeb8d5 | 18-Jun-2024 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
media: hantro: Disable multicore support
Avoid exposing equal Hantro video codecs to userspace. Equal video
codecs allow scheduling work between the cores. For that kernel support
is required, which
media: hantro: Disable multicore support
Avoid exposing equal Hantro video codecs to userspace. Equal video
codecs allow scheduling work between the cores. For that kernel support
is required, which does not yet exist. Until that is implemented avoid
exposing each core separately to userspace so that multicore can be
added in the future without breaking userspace ABI.
This was written with Rockchip RK3588 in mind (which has 4 Hantro H1
cores), but applies to all SoCs.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| 5423e2d2 | 16-May-2024 |
Benjamin Gaignard <benjamin.gaignard@collabora.com> |
media: verisilicon: Add reference buffer compression feature
Reference frame compression is a feature added in the G2 decoder to
compress frame buffers so that the bandwidth of storing/loading
refer
media: verisilicon: Add reference buffer compression feature
Reference frame compression is a feature added in the G2 decoder to
compress frame buffers so that the bandwidth of storing/loading
reference frames can be reduced, especially with high resolution decoded
streams.
The impact of compressed frames is confirmed when using perf to monitor
the number of memory accesses with or without the compression feature.
The following command:
perf stat -a -e \
imx8_ddr0/cycles/,imx8_ddr0/read-cycles/,imx8_ddr0/write-cycles/ \
gst-launch-1.0 filesrc \
location=Jockey_3840x2160_120fps_420_8bit_HEVC_RAW.hevc ! queue ! \
h265parse ! v4l2slh265dec ! video/x-raw,format=NV12 ! fakesink
Gives us these results without the compression feature:
Performance counter stats for 'system wide':
1711300345 imx8_ddr0/cycles/
892207924 imx8_ddr0/read-cycles/
1291785864 imx8_ddr0/write-cycles/
13.760048353 seconds time elapsed
With the compression feature:
Performance counter stats for 'system wide':
274526799 imx8_ddr0/cycles/
453120194 imx8_ddr0/read-cycles/
833391434 imx8_ddr0/write-cycles/
18.257831534 seconds time elapsed
As expected the number of read/write cycles are really lower when
compression is used.
Since storing the compression data requires more memory a module
parameter named 'hevc_use_compression' is used to enable/disable
this feature and, by default, compression isn't used.
Enabling the compression feature means that the output-frames of the
decoder
are stored with a specific compression pixel-format. Since this
pixel format is unknown, this patch restrains the compression feature
usage to the cases where post-processor pixel-formats (NV12 or NV15)
are selected by the applications.
The Fluster compliance HEVC test suite score is still 141/147 with this
patch.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| f579c748 | 21-Jun-2024 |
Alexander Stein <alexander.stein@ew.tq-group.com> |
media: verisilicon: Move Rockchip AV1 hardware drivers to the corresponding option
There is no need to compile the Rockchip specific AV1 drivers if
CONFIG_VIDEO_HANTRO_ROCKCHIP is not set.
All the d
media: verisilicon: Move Rockchip AV1 hardware drivers to the corresponding option
There is no need to compile the Rockchip specific AV1 drivers if
CONFIG_VIDEO_HANTRO_ROCKCHIP is not set.
All the driver functions are only referenced by rockchip_vpu_hw.c which
is already under this option.
Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
Fixes: d8ebe59e7b36 ("media: verisilicon: Add film grain feature to AV1 driver")
Fixes: c0d0e579db4e ("media: verisilicon: Add AV1 entropy helpers")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| 3e5111c5 | 21-Jun-2024 |
Alexander Stein <alexander.stein@ew.tq-group.com> |
media: verisilicon: Move Rockchip hardware drivers to the corresponding option
There is no need to compile the Rockchip specific drivers if
CONFIG_VIDEO_HANTRO_ROCKCHIP is not set.
All the driver fu
media: verisilicon: Move Rockchip hardware drivers to the corresponding option
There is no need to compile the Rockchip specific drivers if
CONFIG_VIDEO_HANTRO_ROCKCHIP is not set.
All the driver functions are only referenced by rockchip_vpu_hw.c which
is already under this option.
Fixes: c9caebd57b3a ("media: hantro: merge Rockchip platform drivers")
Fixes: c07665f99386 ("media: hantro: Add H.264 support for Rockchip VDPU2")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| 2038c321 | 21-May-2024 |
Benjamin Gaignard <benjamin.gaignard@collabora.com> |
media: verisilicon: AV1: Correct some sizes/positions on register fields
Some fields aren't well positioned or with an incorrect size inside the
hardware registers. Fix them.
This doesn't impact th
media: verisilicon: AV1: Correct some sizes/positions on register fields
Some fields aren't well positioned or with an incorrect size inside the
hardware registers. Fix them.
This doesn't impact the Fluster score.
Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| 65e9f52f | 28-Mar-2024 |
Benjamin Gaignard <benjamin.gaignard@collabora.com> |
media: verisilicon: Fix auxiliary buffer allocation size
Use v4l2_av1_tile_info->tile_cols to get the number of columns
in the frame and make auxiliary buffer memory size computation
more accurate.
media: verisilicon: Fix auxiliary buffer allocation size
Use v4l2_av1_tile_info->tile_cols to get the number of columns
in the frame and make auxiliary buffer memory size computation
more accurate.
Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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| 5c883a70 | 16-Nov-2023 |
Andrzej Pietrasiewicz <andrzej.p@collabora.com> |
media: verisilicon: Correct a typo in H1_REG_MAD_CTRL_MAD_THRESHOLD
It's a THRESHOLD and not a THREDHOLD.
Link: https://lore.kernel.org/linux-media/20231116154816.70959-3-andrzej.p@collabora.com
Si
media: verisilicon: Correct a typo in H1_REG_MAD_CTRL_MAD_THRESHOLD
It's a THRESHOLD and not a THREDHOLD.
Link: https://lore.kernel.org/linux-media/20231116154816.70959-3-andrzej.p@collabora.com
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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| b0fb9ca3 | 10-Jan-2024 |
Hugues Fruchet <hugues.fruchet@foss.st.com> |
media: hantro: add support for STM32MP25 VENC
Add support for STM32MP25 VENC video hardware encoder.
Support of JPEG encoding.
VENC has its own reset/clock/irq.
Reviewed-by: Nicolas Dufresne <nicol
media: hantro: add support for STM32MP25 VENC
Add support for STM32MP25 VENC video hardware encoder.
Support of JPEG encoding.
VENC has its own reset/clock/irq.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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