1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Maxim GMSL2 Deserializer Driver 4 * 5 * Copyright (C) 2024 Collabora Ltd. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/fwnode.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/i2c-mux.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-fwnode.h> 22 #include <media/v4l2-subdev.h> 23 24 #define MAX96714_DEVICE_ID 0xc9 25 #define MAX96714F_DEVICE_ID 0xca 26 #define MAX96714_NPORTS 2 27 #define MAX96714_PAD_SINK 0 28 #define MAX96714_PAD_SOURCE 1 29 #define MAX96714_CSI_NLANES 4 30 31 /* DEV */ 32 #define MAX96714_REG13 CCI_REG8(0x0d) 33 #define MAX96714_DEV_REV CCI_REG8(0x0e) 34 #define MAX96714_DEV_REV_MASK GENMASK(3, 0) 35 #define MAX96714_LINK_LOCK CCI_REG8(0x13) 36 #define MAX96714_LINK_LOCK_BIT BIT(3) 37 #define MAX96714_IO_CHK0 CCI_REG8(0x38) 38 #define MAX96714_PATTERN_CLK_FREQ GENMASK(1, 0) 39 /* VID_RX */ 40 #define MAX96714_VIDEO_RX8 CCI_REG8(0x11a) 41 #define MAX96714_VID_LOCK BIT(6) 42 43 /* VRX_PATGEN_0 */ 44 #define MAX96714_PATGEN_0 CCI_REG8(0x240) 45 #define MAX96714_PATGEN_1 CCI_REG8(0x241) 46 #define MAX96714_PATGEN_MODE GENMASK(5, 4) 47 #define MAX96714_PATGEN_VS_DLY CCI_REG24(0x242) 48 #define MAX96714_PATGEN_VS_HIGH CCI_REG24(0x245) 49 #define MAX96714_PATGEN_VS_LOW CCI_REG24(0x248) 50 #define MAX96714_PATGEN_V2H CCI_REG24(0x24b) 51 #define MAX96714_PATGEN_HS_HIGH CCI_REG16(0x24e) 52 #define MAX96714_PATGEN_HS_LOW CCI_REG16(0x250) 53 #define MAX96714_PATGEN_HS_CNT CCI_REG16(0x252) 54 #define MAX96714_PATGEN_V2D CCI_REG24(0x254) 55 #define MAX96714_PATGEN_DE_HIGH CCI_REG16(0x257) 56 #define MAX96714_PATGEN_DE_LOW CCI_REG16(0x259) 57 #define MAX96714_PATGEN_DE_CNT CCI_REG16(0x25b) 58 #define MAX96714_PATGEN_GRAD_INC CCI_REG8(0x25d) 59 #define MAX96714_PATGEN_CHKB_COLOR_A CCI_REG24(0x25e) 60 #define MAX96714_PATGEN_CHKB_COLOR_B CCI_REG24(0x261) 61 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264) 62 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265) 63 #define MAX96714_PATGEN_CHKB_ALT CCI_REG8(0x266) 64 /* BACKTOP */ 65 #define MAX96714_BACKTOP25 CCI_REG8(0x320) 66 #define CSI_DPLL_FREQ_MASK GENMASK(4, 0) 67 68 /* MIPI_PHY */ 69 #define MAX96714_MIPI_PHY0 CCI_REG8(0x330) 70 #define MAX96714_FORCE_CSI_OUT BIT(7) 71 #define MAX96714_MIPI_STDBY_N CCI_REG8(0x332) 72 #define MAX96714_MIPI_STDBY_MASK GENMASK(5, 4) 73 #define MAX96714_MIPI_LANE_MAP CCI_REG8(0x333) 74 #define MAX96714_MIPI_POLARITY CCI_REG8(0x335) 75 #define MAX96714_MIPI_POLARITY_MASK GENMASK(5, 0) 76 77 /* MIPI_TX */ 78 #define MAX96714_MIPI_LANE_CNT CCI_REG8(0x44a) 79 #define MAX96714_CSI2_LANE_CNT_MASK GENMASK(7, 6) 80 #define MAX96714_MIPI_TX52 CCI_REG8(0x474) 81 #define MAX96714_TUN_EN BIT(0) 82 83 #define MHZ(v) ((u32)((v) * 1000000U)) 84 85 enum max96714_vpg_mode { 86 MAX96714_VPG_DISABLED = 0, 87 MAX96714_VPG_CHECKERBOARD = 1, 88 MAX96714_VPG_GRADIENT = 2, 89 }; 90 91 struct max96714_rxport { 92 struct { 93 struct v4l2_subdev *sd; 94 u16 pad; 95 struct fwnode_handle *ep_fwnode; 96 } source; 97 struct regulator *poc; 98 }; 99 100 struct max96714_txport { 101 struct v4l2_fwnode_endpoint vep; 102 }; 103 104 struct max96714_priv { 105 struct i2c_client *client; 106 struct regmap *regmap; 107 struct gpio_desc *pd_gpio; 108 struct max96714_rxport rxport; 109 struct i2c_mux_core *mux; 110 u64 enabled_source_streams; 111 struct v4l2_subdev sd; 112 struct media_pad pads[MAX96714_NPORTS]; 113 struct v4l2_mbus_config_mipi_csi2 mipi_csi2; 114 struct v4l2_ctrl_handler ctrl_handler; 115 struct v4l2_async_notifier notifier; 116 s64 tx_link_freq; 117 enum max96714_vpg_mode pattern; 118 }; 119 120 static inline struct max96714_priv *sd_to_max96714(struct v4l2_subdev *sd) 121 { 122 return container_of(sd, struct max96714_priv, sd); 123 } 124 125 static int max96714_enable_tx_port(struct max96714_priv *priv) 126 { 127 return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N, 128 MAX96714_MIPI_STDBY_MASK, 129 MAX96714_MIPI_STDBY_MASK, NULL); 130 } 131 132 static int max96714_disable_tx_port(struct max96714_priv *priv) 133 { 134 return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N, 135 MAX96714_MIPI_STDBY_MASK, 0, NULL); 136 } 137 138 static bool max96714_tx_port_enabled(struct max96714_priv *priv) 139 { 140 u64 val; 141 142 cci_read(priv->regmap, MAX96714_MIPI_STDBY_N, &val, NULL); 143 144 return val & MAX96714_MIPI_STDBY_MASK; 145 } 146 147 static int max96714_apply_patgen_timing(struct max96714_priv *priv, 148 struct v4l2_subdev_state *state) 149 { 150 struct v4l2_mbus_framefmt *fmt = 151 v4l2_subdev_state_get_format(state, MAX96714_PAD_SOURCE); 152 const u32 h_active = fmt->width; 153 const u32 h_fp = 88; 154 const u32 h_sw = 44; 155 const u32 h_bp = 148; 156 u32 h_tot; 157 const u32 v_active = fmt->height; 158 const u32 v_fp = 4; 159 const u32 v_sw = 5; 160 const u32 v_bp = 36; 161 u32 v_tot; 162 int ret = 0; 163 164 h_tot = h_active + h_fp + h_sw + h_bp; 165 v_tot = v_active + v_fp + v_sw + v_bp; 166 167 /* 75 Mhz pixel clock */ 168 cci_update_bits(priv->regmap, MAX96714_IO_CHK0, 169 MAX96714_PATTERN_CLK_FREQ, 1, &ret); 170 171 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height, 172 fmt->width); 173 174 cci_write(priv->regmap, MAX96714_PATGEN_VS_DLY, 0, &ret); 175 cci_write(priv->regmap, MAX96714_PATGEN_VS_HIGH, v_sw * h_tot, &ret); 176 cci_write(priv->regmap, MAX96714_PATGEN_VS_LOW, 177 (v_active + v_fp + v_bp) * h_tot, &ret); 178 cci_write(priv->regmap, MAX96714_PATGEN_HS_HIGH, h_sw, &ret); 179 cci_write(priv->regmap, MAX96714_PATGEN_HS_LOW, h_active + h_fp + h_bp, 180 &ret); 181 cci_write(priv->regmap, MAX96714_PATGEN_V2D, 182 h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret); 183 cci_write(priv->regmap, MAX96714_PATGEN_HS_CNT, v_tot, &ret); 184 cci_write(priv->regmap, MAX96714_PATGEN_DE_HIGH, h_active, &ret); 185 cci_write(priv->regmap, MAX96714_PATGEN_DE_LOW, h_fp + h_sw + h_bp, 186 &ret); 187 cci_write(priv->regmap, MAX96714_PATGEN_DE_CNT, v_active, &ret); 188 /* B G R */ 189 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_A, 0xfecc00, &ret); 190 /* B G R */ 191 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_B, 0x006aa7, &ret); 192 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_A, 0x3c, &ret); 193 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_B, 0x3c, &ret); 194 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_ALT, 0x3c, &ret); 195 cci_write(priv->regmap, MAX96714_PATGEN_GRAD_INC, 0x10, &ret); 196 197 return ret; 198 } 199 200 static int max96714_apply_patgen(struct max96714_priv *priv, 201 struct v4l2_subdev_state *state) 202 { 203 unsigned int val; 204 int ret = 0; 205 206 if (priv->pattern) 207 ret = max96714_apply_patgen_timing(priv, state); 208 209 cci_write(priv->regmap, MAX96714_PATGEN_0, priv->pattern ? 0xfb : 0, 210 &ret); 211 212 val = FIELD_PREP(MAX96714_PATGEN_MODE, priv->pattern); 213 cci_update_bits(priv->regmap, MAX96714_PATGEN_1, MAX96714_PATGEN_MODE, 214 val, &ret); 215 return ret; 216 } 217 218 static int max96714_s_ctrl(struct v4l2_ctrl *ctrl) 219 { 220 struct max96714_priv *priv = 221 container_of(ctrl->handler, struct max96714_priv, ctrl_handler); 222 int ret; 223 224 switch (ctrl->id) { 225 case V4L2_CID_TEST_PATTERN: 226 if (priv->enabled_source_streams) 227 return -EBUSY; 228 priv->pattern = ctrl->val; 229 break; 230 default: 231 return -EINVAL; 232 } 233 234 ret = cci_update_bits(priv->regmap, MAX96714_MIPI_PHY0, 235 MAX96714_FORCE_CSI_OUT, 236 priv->pattern ? MAX96714_FORCE_CSI_OUT : 0, NULL); 237 238 /* Pattern generator doesn't work with tunnel mode */ 239 return cci_update_bits(priv->regmap, MAX96714_MIPI_TX52, 240 MAX96714_TUN_EN, 241 priv->pattern ? 0 : MAX96714_TUN_EN, &ret); 242 } 243 244 static const char * const max96714_test_pattern[] = { 245 "Disabled", 246 "Checkerboard", 247 "Gradient" 248 }; 249 250 static const struct v4l2_ctrl_ops max96714_ctrl_ops = { 251 .s_ctrl = max96714_s_ctrl, 252 }; 253 254 static int max96714_enable_streams(struct v4l2_subdev *sd, 255 struct v4l2_subdev_state *state, 256 u32 source_pad, u64 streams_mask) 257 { 258 struct max96714_priv *priv = sd_to_max96714(sd); 259 u64 sink_streams; 260 int ret; 261 262 if (!priv->enabled_source_streams) 263 max96714_enable_tx_port(priv); 264 265 ret = max96714_apply_patgen(priv, state); 266 if (ret) 267 goto err; 268 269 if (!priv->pattern) { 270 if (!priv->rxport.source.sd) { 271 ret = -ENODEV; 272 goto err; 273 } 274 275 sink_streams = 276 v4l2_subdev_state_xlate_streams(state, 277 MAX96714_PAD_SOURCE, 278 MAX96714_PAD_SINK, 279 &streams_mask); 280 281 ret = v4l2_subdev_enable_streams(priv->rxport.source.sd, 282 priv->rxport.source.pad, 283 sink_streams); 284 if (ret) 285 goto err; 286 } 287 288 priv->enabled_source_streams |= streams_mask; 289 290 return 0; 291 292 err: 293 if (!priv->enabled_source_streams) 294 max96714_disable_tx_port(priv); 295 296 return ret; 297 } 298 299 static int max96714_disable_streams(struct v4l2_subdev *sd, 300 struct v4l2_subdev_state *state, 301 u32 source_pad, u64 streams_mask) 302 { 303 struct max96714_priv *priv = sd_to_max96714(sd); 304 u64 sink_streams; 305 306 if (!priv->pattern) { 307 int ret; 308 309 sink_streams = 310 v4l2_subdev_state_xlate_streams(state, 311 MAX96714_PAD_SOURCE, 312 MAX96714_PAD_SINK, 313 &streams_mask); 314 315 ret = v4l2_subdev_disable_streams(priv->rxport.source.sd, 316 priv->rxport.source.pad, 317 sink_streams); 318 if (ret) 319 return ret; 320 } 321 322 priv->enabled_source_streams &= ~streams_mask; 323 324 if (!priv->enabled_source_streams) 325 max96714_disable_tx_port(priv); 326 327 return 0; 328 } 329 330 static int max96714_set_fmt(struct v4l2_subdev *sd, 331 struct v4l2_subdev_state *state, 332 struct v4l2_subdev_format *format) 333 { 334 struct max96714_priv *priv = sd_to_max96714(sd); 335 struct v4l2_mbus_framefmt *fmt; 336 337 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 338 priv->enabled_source_streams) 339 return -EBUSY; 340 341 /* No transcoding, source and sink formats must match. */ 342 if (format->pad == MAX96714_PAD_SOURCE) 343 return v4l2_subdev_get_fmt(sd, state, format); 344 345 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 346 if (!fmt) 347 return -EINVAL; 348 349 *fmt = format->format; 350 351 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 352 format->stream); 353 if (!fmt) 354 return -EINVAL; 355 356 *fmt = format->format; 357 358 return 0; 359 } 360 361 static int _max96714_set_routing(struct v4l2_subdev *sd, 362 struct v4l2_subdev_state *state, 363 enum v4l2_subdev_format_whence which, 364 struct v4l2_subdev_krouting *routing) 365 { 366 static const struct v4l2_mbus_framefmt format = { 367 .width = 1280, 368 .height = 1080, 369 .code = MEDIA_BUS_FMT_Y8_1X8, 370 .field = V4L2_FIELD_NONE, 371 }; 372 int ret; 373 374 /* 375 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until 376 * frame desc is made dynamically allocated. 377 */ 378 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX) 379 return -EINVAL; 380 381 ret = v4l2_subdev_routing_validate(sd, routing, 382 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 383 if (ret) 384 return ret; 385 386 return v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 387 } 388 389 static int max96714_set_routing(struct v4l2_subdev *sd, 390 struct v4l2_subdev_state *state, 391 enum v4l2_subdev_format_whence which, 392 struct v4l2_subdev_krouting *routing) 393 { 394 struct max96714_priv *priv = sd_to_max96714(sd); 395 396 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 397 return -EBUSY; 398 399 return _max96714_set_routing(sd, state, which, routing); 400 } 401 402 static int max96714_init_state(struct v4l2_subdev *sd, 403 struct v4l2_subdev_state *state) 404 { 405 struct v4l2_subdev_route routes[] = { 406 { 407 .sink_pad = MAX96714_PAD_SINK, 408 .sink_stream = 0, 409 .source_pad = MAX96714_PAD_SOURCE, 410 .source_stream = 0, 411 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 412 } 413 }; 414 struct v4l2_subdev_krouting routing = { 415 .num_routes = ARRAY_SIZE(routes), 416 .routes = routes, 417 }; 418 419 return _max96714_set_routing(sd, state, V4L2_SUBDEV_FORMAT_ACTIVE, 420 &routing); 421 } 422 423 static const struct v4l2_subdev_pad_ops max96714_pad_ops = { 424 .enable_streams = max96714_enable_streams, 425 .disable_streams = max96714_disable_streams, 426 427 .set_routing = max96714_set_routing, 428 .get_fmt = v4l2_subdev_get_fmt, 429 .set_fmt = max96714_set_fmt, 430 }; 431 432 static bool max96714_link_locked(struct max96714_priv *priv) 433 { 434 u64 val = 0; 435 436 cci_read(priv->regmap, MAX96714_LINK_LOCK, &val, NULL); 437 438 return val & MAX96714_LINK_LOCK_BIT; 439 } 440 441 static void max96714_link_status(struct max96714_priv *priv) 442 { 443 struct device *dev = &priv->client->dev; 444 445 dev_info(dev, "Link locked:%d\n", max96714_link_locked(priv)); 446 } 447 448 static bool max96714_pipe_locked(struct max96714_priv *priv) 449 { 450 u64 val; 451 452 cci_read(priv->regmap, MAX96714_VIDEO_RX8, &val, NULL); 453 454 return val & MAX96714_VID_LOCK; 455 } 456 457 static void max96714_pipe_status(struct max96714_priv *priv) 458 { 459 struct device *dev = &priv->client->dev; 460 461 dev_info(dev, "Pipe vidlock:%d\n", max96714_pipe_locked(priv)); 462 } 463 464 static void max96714_csi_status(struct max96714_priv *priv) 465 { 466 struct device *dev = &priv->client->dev; 467 u64 freq = 0; 468 469 cci_read(priv->regmap, MAX96714_BACKTOP25, &freq, NULL); 470 freq = FIELD_GET(CSI_DPLL_FREQ_MASK, freq); 471 472 dev_info(dev, "CSI controller DPLL freq:%u00MHz CSIPHY enabled:%d\n", 473 (u8)freq, max96714_tx_port_enabled(priv)); 474 } 475 476 static int max96714_log_status(struct v4l2_subdev *sd) 477 { 478 struct max96714_priv *priv = sd_to_max96714(sd); 479 struct device *dev = &priv->client->dev; 480 481 dev_info(dev, "Deserializer: max96714\n"); 482 483 max96714_link_status(priv); 484 max96714_pipe_status(priv); 485 max96714_csi_status(priv); 486 487 return 0; 488 } 489 490 static const struct v4l2_subdev_core_ops max96714_subdev_core_ops = { 491 .log_status = max96714_log_status, 492 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 493 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 494 }; 495 496 static const struct v4l2_subdev_video_ops max96714_video_ops = { 497 .s_stream = v4l2_subdev_s_stream_helper, 498 }; 499 500 static const struct v4l2_subdev_internal_ops max96714_internal_ops = { 501 .init_state = max96714_init_state, 502 }; 503 504 static const struct v4l2_subdev_ops max96714_subdev_ops = { 505 .video = &max96714_video_ops, 506 .core = &max96714_subdev_core_ops, 507 .pad = &max96714_pad_ops, 508 }; 509 510 static const struct media_entity_operations max96714_entity_ops = { 511 .link_validate = v4l2_subdev_link_validate, 512 }; 513 514 static int max96714_notify_bound(struct v4l2_async_notifier *notifier, 515 struct v4l2_subdev *subdev, 516 struct v4l2_async_connection *asd) 517 { 518 struct max96714_priv *priv = sd_to_max96714(notifier->sd); 519 struct device *dev = &priv->client->dev; 520 int ret; 521 522 ret = media_entity_get_fwnode_pad(&subdev->entity, 523 priv->rxport.source.ep_fwnode, 524 MEDIA_PAD_FL_SOURCE); 525 if (ret < 0) { 526 dev_err(dev, "Failed to find pad for %s\n", subdev->name); 527 return ret; 528 } 529 530 priv->rxport.source.sd = subdev; 531 priv->rxport.source.pad = ret; 532 533 ret = media_create_pad_link(&priv->rxport.source.sd->entity, 534 priv->rxport.source.pad, &priv->sd.entity, 535 MAX96714_PAD_SINK, 536 MEDIA_LNK_FL_ENABLED | 537 MEDIA_LNK_FL_IMMUTABLE); 538 if (ret) { 539 dev_err(dev, "Unable to link %s:%u -> %s:%u\n", 540 priv->rxport.source.sd->name, priv->rxport.source.pad, 541 priv->sd.name, MAX96714_PAD_SINK); 542 return ret; 543 } 544 545 return 0; 546 } 547 548 static const struct v4l2_async_notifier_operations max96714_notify_ops = { 549 .bound = max96714_notify_bound, 550 }; 551 552 static int max96714_v4l2_notifier_register(struct max96714_priv *priv) 553 { 554 struct device *dev = &priv->client->dev; 555 struct max96714_rxport *rxport = &priv->rxport; 556 struct v4l2_async_connection *asd; 557 int ret; 558 559 if (!rxport->source.ep_fwnode) 560 return 0; 561 562 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 563 564 asd = v4l2_async_nf_add_fwnode(&priv->notifier, 565 rxport->source.ep_fwnode, 566 struct v4l2_async_connection); 567 if (IS_ERR(asd)) { 568 dev_err(dev, "Failed to add subdev: %pe", asd); 569 v4l2_async_nf_cleanup(&priv->notifier); 570 return PTR_ERR(asd); 571 } 572 573 priv->notifier.ops = &max96714_notify_ops; 574 575 ret = v4l2_async_nf_register(&priv->notifier); 576 if (ret) { 577 dev_err(dev, "Failed to register subdev_notifier"); 578 v4l2_async_nf_cleanup(&priv->notifier); 579 return ret; 580 } 581 582 return 0; 583 } 584 585 static int max96714_create_subdev(struct max96714_priv *priv) 586 { 587 struct device *dev = &priv->client->dev; 588 int ret; 589 590 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96714_subdev_ops); 591 priv->sd.internal_ops = &max96714_internal_ops; 592 593 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1); 594 priv->sd.ctrl_handler = &priv->ctrl_handler; 595 596 v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ, 597 0, 0, &priv->tx_link_freq); 598 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, 599 &max96714_ctrl_ops, 600 V4L2_CID_TEST_PATTERN, 601 ARRAY_SIZE(max96714_test_pattern) - 1, 602 0, 0, max96714_test_pattern); 603 if (priv->ctrl_handler.error) { 604 ret = priv->ctrl_handler.error; 605 goto err_free_ctrl; 606 } 607 608 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 609 V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS; 610 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 611 priv->sd.entity.ops = &max96714_entity_ops; 612 613 priv->pads[MAX96714_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 614 priv->pads[MAX96714_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 615 616 ret = media_entity_pads_init(&priv->sd.entity, 617 MAX96714_NPORTS, 618 priv->pads); 619 if (ret) 620 goto err_free_ctrl; 621 622 priv->sd.state_lock = priv->sd.ctrl_handler->lock; 623 624 ret = v4l2_subdev_init_finalize(&priv->sd); 625 if (ret) 626 goto err_entity_cleanup; 627 628 ret = max96714_v4l2_notifier_register(priv); 629 if (ret) { 630 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret); 631 goto err_subdev_cleanup; 632 } 633 634 ret = v4l2_async_register_subdev(&priv->sd); 635 if (ret) { 636 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret); 637 goto err_unreg_notif; 638 } 639 640 return 0; 641 642 err_unreg_notif: 643 v4l2_async_nf_unregister(&priv->notifier); 644 v4l2_async_nf_cleanup(&priv->notifier); 645 err_subdev_cleanup: 646 v4l2_subdev_cleanup(&priv->sd); 647 err_entity_cleanup: 648 media_entity_cleanup(&priv->sd.entity); 649 err_free_ctrl: 650 v4l2_ctrl_handler_free(&priv->ctrl_handler); 651 652 return ret; 653 }; 654 655 static void max96714_destroy_subdev(struct max96714_priv *priv) 656 { 657 v4l2_async_nf_unregister(&priv->notifier); 658 v4l2_async_nf_cleanup(&priv->notifier); 659 v4l2_async_unregister_subdev(&priv->sd); 660 661 v4l2_subdev_cleanup(&priv->sd); 662 663 media_entity_cleanup(&priv->sd.entity); 664 v4l2_ctrl_handler_free(&priv->ctrl_handler); 665 } 666 667 static int max96714_i2c_mux_select(struct i2c_mux_core *mux, u32 chan) 668 { 669 return 0; 670 } 671 672 static int max96714_i2c_mux_init(struct max96714_priv *priv) 673 { 674 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 675 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE, 676 max96714_i2c_mux_select, NULL); 677 if (!priv->mux) 678 return -ENOMEM; 679 680 return i2c_mux_add_adapter(priv->mux, 0, 0); 681 } 682 683 static int max96714_init_tx_port(struct max96714_priv *priv) 684 { 685 struct v4l2_mbus_config_mipi_csi2 *mipi; 686 unsigned long lanes_used = 0; 687 unsigned int val, lane; 688 int ret; 689 690 ret = max96714_disable_tx_port(priv); 691 692 mipi = &priv->mipi_csi2; 693 val = div_u64(priv->tx_link_freq * 2, MHZ(100)); 694 695 cci_update_bits(priv->regmap, MAX96714_BACKTOP25, 696 CSI_DPLL_FREQ_MASK, val, &ret); 697 698 val = FIELD_PREP(MAX96714_CSI2_LANE_CNT_MASK, mipi->num_data_lanes - 1); 699 cci_update_bits(priv->regmap, MAX96714_MIPI_LANE_CNT, 700 MAX96714_CSI2_LANE_CNT_MASK, val, &ret); 701 702 /* lanes polarity */ 703 val = 0; 704 for (lane = 0; lane < mipi->num_data_lanes + 1; lane++) { 705 if (!mipi->lane_polarities[lane]) 706 continue; 707 if (lane == 0) 708 /* clock lane */ 709 val |= BIT(5); 710 else if (lane < 3) 711 /* Lane D0 and D1 */ 712 val |= BIT(lane - 1); 713 else 714 /* D2 and D3 */ 715 val |= BIT(lane); 716 } 717 718 cci_update_bits(priv->regmap, MAX96714_MIPI_POLARITY, 719 MAX96714_MIPI_POLARITY_MASK, val, &ret); 720 721 /* lanes mapping */ 722 val = 0; 723 for (lane = 0; lane < mipi->num_data_lanes; lane++) { 724 val |= (mipi->data_lanes[lane] - 1) << (lane * 2); 725 lanes_used |= BIT(mipi->data_lanes[lane] - 1); 726 } 727 728 /* 729 * Unused lanes need to be mapped as well to not have 730 * the same lanes mapped twice. 731 */ 732 for (; lane < MAX96714_CSI_NLANES; lane++) { 733 unsigned int idx = find_first_zero_bit(&lanes_used, 734 MAX96714_CSI_NLANES); 735 736 val |= idx << (lane * 2); 737 lanes_used |= BIT(idx); 738 } 739 740 return cci_write(priv->regmap, MAX96714_MIPI_LANE_MAP, val, &ret); 741 } 742 743 static int max96714_rxport_enable_poc(struct max96714_priv *priv) 744 { 745 struct max96714_rxport *rxport = &priv->rxport; 746 747 if (!rxport->poc) 748 return 0; 749 750 return regulator_enable(rxport->poc); 751 } 752 753 static int max96714_rxport_disable_poc(struct max96714_priv *priv) 754 { 755 struct max96714_rxport *rxport = &priv->rxport; 756 757 if (!rxport->poc) 758 return 0; 759 760 return regulator_disable(rxport->poc); 761 } 762 763 static int max96714_parse_dt_txport(struct max96714_priv *priv) 764 { 765 struct device *dev = &priv->client->dev; 766 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 767 struct fwnode_handle *ep_fwnode; 768 u32 num_data_lanes; 769 int ret; 770 771 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 772 MAX96714_PAD_SOURCE, 0, 0); 773 if (!ep_fwnode) 774 return -EINVAL; 775 776 ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep); 777 fwnode_handle_put(ep_fwnode); 778 if (ret) { 779 dev_err(dev, "tx: failed to parse endpoint data\n"); 780 return -EINVAL; 781 } 782 783 if (vep.nr_of_link_frequencies != 1) { 784 ret = -EINVAL; 785 goto err_free_vep; 786 } 787 788 priv->tx_link_freq = vep.link_frequencies[0]; 789 /* Min 50MHz, Max 1250MHz, 50MHz step */ 790 if (priv->tx_link_freq < MHZ(50) || priv->tx_link_freq > MHZ(1250) || 791 (u32)priv->tx_link_freq % MHZ(50)) { 792 dev_err(dev, "tx: invalid link frequency\n"); 793 ret = -EINVAL; 794 goto err_free_vep; 795 } 796 797 num_data_lanes = vep.bus.mipi_csi2.num_data_lanes; 798 if (num_data_lanes < 1 || num_data_lanes > MAX96714_CSI_NLANES) { 799 dev_err(dev, 800 "tx: invalid number of data lanes must be 1 to 4\n"); 801 ret = -EINVAL; 802 goto err_free_vep; 803 } 804 805 priv->mipi_csi2 = vep.bus.mipi_csi2; 806 807 err_free_vep: 808 v4l2_fwnode_endpoint_free(&vep); 809 810 return ret; 811 } 812 813 static int max96714_parse_dt_rxport(struct max96714_priv *priv) 814 { 815 static const char *poc_name = "port0-poc"; 816 struct max96714_rxport *rxport = &priv->rxport; 817 struct device *dev = &priv->client->dev; 818 struct fwnode_handle *ep_fwnode; 819 int ret; 820 821 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 822 MAX96714_PAD_SINK, 0, 0); 823 if (!ep_fwnode) 824 return -ENOENT; 825 826 rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode); 827 fwnode_handle_put(ep_fwnode); 828 829 if (!rxport->source.ep_fwnode) { 830 dev_err(dev, "rx: no remote endpoint\n"); 831 return -EINVAL; 832 } 833 834 rxport->poc = devm_regulator_get_optional(dev, poc_name); 835 if (IS_ERR(rxport->poc)) { 836 ret = PTR_ERR(rxport->poc); 837 if (ret == -ENODEV) { 838 rxport->poc = NULL; 839 } else { 840 dev_err(dev, "rx: failed to get POC supply: %d\n", ret); 841 goto err_put_source_ep_fwnode; 842 } 843 } 844 845 return 0; 846 847 err_put_source_ep_fwnode: 848 fwnode_handle_put(rxport->source.ep_fwnode); 849 return ret; 850 } 851 852 static int max96714_parse_dt(struct max96714_priv *priv) 853 { 854 int ret; 855 856 ret = max96714_parse_dt_txport(priv); 857 if (ret) 858 return ret; 859 860 ret = max96714_parse_dt_rxport(priv); 861 /* 862 * The deserializer can create a test pattern even if the 863 * rx port is not connected to a serializer. 864 */ 865 if (ret && ret == -ENOENT) 866 ret = 0; 867 868 return ret; 869 } 870 871 static int max96714_enable_core_hw(struct max96714_priv *priv) 872 { 873 struct device *dev = &priv->client->dev; 874 u64 val; 875 int ret; 876 877 if (priv->pd_gpio) { 878 /* wait min 2 ms for reset to complete */ 879 gpiod_set_value_cansleep(priv->pd_gpio, 1); 880 fsleep(2000); 881 gpiod_set_value_cansleep(priv->pd_gpio, 0); 882 /* wait min 2 ms for power up to finish */ 883 fsleep(2000); 884 } 885 886 ret = cci_read(priv->regmap, MAX96714_REG13, &val, NULL); 887 if (ret) { 888 dev_err_probe(dev, ret, "Cannot read first register, abort\n"); 889 goto err_pd_gpio; 890 } 891 892 if (val != MAX96714_DEVICE_ID && val != MAX96714F_DEVICE_ID) { 893 dev_err(dev, "Unsupported device id expected %x got %x\n", 894 MAX96714F_DEVICE_ID, (u8)val); 895 ret = -EOPNOTSUPP; 896 goto err_pd_gpio; 897 } 898 899 ret = cci_read(priv->regmap, MAX96714_DEV_REV, &val, NULL); 900 if (ret) 901 goto err_pd_gpio; 902 903 dev_dbg(dev, "Found %x (rev %lx)\n", MAX96714F_DEVICE_ID, 904 (u8)val & MAX96714_DEV_REV_MASK); 905 906 ret = cci_read(priv->regmap, MAX96714_MIPI_TX52, &val, NULL); 907 if (ret) 908 goto err_pd_gpio; 909 910 if (!(val & MAX96714_TUN_EN)) { 911 dev_err(dev, "Only supporting tunnel mode"); 912 ret = -EOPNOTSUPP; 913 goto err_pd_gpio; 914 } 915 916 return 0; 917 918 err_pd_gpio: 919 gpiod_set_value_cansleep(priv->pd_gpio, 1); 920 return ret; 921 } 922 923 static void max96714_disable_core_hw(struct max96714_priv *priv) 924 { 925 gpiod_set_value_cansleep(priv->pd_gpio, 1); 926 } 927 928 static int max96714_get_hw_resources(struct max96714_priv *priv) 929 { 930 struct device *dev = &priv->client->dev; 931 932 priv->regmap = devm_cci_regmap_init_i2c(priv->client, 16); 933 if (IS_ERR(priv->regmap)) 934 return PTR_ERR(priv->regmap); 935 936 priv->pd_gpio = 937 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 938 if (IS_ERR(priv->pd_gpio)) 939 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio), 940 "Cannot get powerdown GPIO\n"); 941 return 0; 942 } 943 944 static int max96714_probe(struct i2c_client *client) 945 { 946 struct device *dev = &client->dev; 947 struct max96714_priv *priv; 948 int ret; 949 950 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 951 if (!priv) 952 return -ENOMEM; 953 954 priv->client = client; 955 956 ret = max96714_get_hw_resources(priv); 957 if (ret) 958 return ret; 959 960 ret = max96714_enable_core_hw(priv); 961 if (ret) 962 return ret; 963 964 ret = max96714_parse_dt(priv); 965 if (ret) 966 goto err_disable_core_hw; 967 968 max96714_init_tx_port(priv); 969 970 ret = max96714_rxport_enable_poc(priv); 971 if (ret) 972 goto err_free_ports; 973 974 ret = max96714_i2c_mux_init(priv); 975 if (ret) 976 goto err_disable_poc; 977 978 ret = max96714_create_subdev(priv); 979 if (ret) 980 goto err_del_mux; 981 982 return 0; 983 984 err_del_mux: 985 i2c_mux_del_adapters(priv->mux); 986 err_disable_poc: 987 max96714_rxport_disable_poc(priv); 988 err_free_ports: 989 fwnode_handle_put(priv->rxport.source.ep_fwnode); 990 err_disable_core_hw: 991 max96714_disable_core_hw(priv); 992 993 return ret; 994 } 995 996 static void max96714_remove(struct i2c_client *client) 997 { 998 struct v4l2_subdev *sd = i2c_get_clientdata(client); 999 struct max96714_priv *priv = sd_to_max96714(sd); 1000 1001 max96714_destroy_subdev(priv); 1002 i2c_mux_del_adapters(priv->mux); 1003 max96714_rxport_disable_poc(priv); 1004 fwnode_handle_put(priv->rxport.source.ep_fwnode); 1005 max96714_disable_core_hw(priv); 1006 gpiod_set_value_cansleep(priv->pd_gpio, 1); 1007 } 1008 1009 static const struct of_device_id max96714_of_ids[] = { 1010 { .compatible = "maxim,max96714f" }, 1011 { } 1012 }; 1013 MODULE_DEVICE_TABLE(of, max96714_of_ids); 1014 1015 static struct i2c_driver max96714_i2c_driver = { 1016 .driver = { 1017 .name = "max96714", 1018 .of_match_table = max96714_of_ids, 1019 }, 1020 .probe = max96714_probe, 1021 .remove = max96714_remove, 1022 }; 1023 1024 module_i2c_driver(max96714_i2c_driver); 1025 1026 MODULE_LICENSE("GPL"); 1027 MODULE_DESCRIPTION("Maxim Integrated GMSL2 Deserializers Driver"); 1028 MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>"); 1029