1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Maxim GMSL2 Serializer Driver 4 * 5 * Copyright (C) 2024 Collabora Ltd. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/fwnode.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-fwnode.h> 22 #include <media/v4l2-subdev.h> 23 24 #define MAX96717_DEVICE_ID 0xbf 25 #define MAX96717F_DEVICE_ID 0xc8 26 #define MAX96717_PORTS 2 27 #define MAX96717_PAD_SINK 0 28 #define MAX96717_PAD_SOURCE 1 29 #define MAX96717_CSI_NLANES 4 30 31 #define MAX96717_DEFAULT_CLKOUT_RATE 24000000UL 32 33 /* DEV */ 34 #define MAX96717_REG3 CCI_REG8(0x3) 35 #define MAX96717_RCLKSEL GENMASK(1, 0) 36 #define RCLKSEL_REF_PLL CCI_REG8(0x3) 37 #define MAX96717_REG6 CCI_REG8(0x6) 38 #define RCLKEN BIT(5) 39 #define MAX96717_DEV_ID CCI_REG8(0xd) 40 #define MAX96717_DEV_REV CCI_REG8(0xe) 41 #define MAX96717_DEV_REV_MASK GENMASK(3, 0) 42 43 /* VID_TX Z */ 44 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110) 45 #define MAX96717_VIDEO_AUTO_BPP BIT(3) 46 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112) 47 #define MAX96717_VIDEO_PCLKDET BIT(7) 48 49 /* VTX_Z */ 50 #define MAX96717_VTX0 CCI_REG8(0x24e) 51 #define MAX96717_VTX1 CCI_REG8(0x24f) 52 #define MAX96717_PATTERN_CLK_FREQ GENMASK(3, 1) 53 #define MAX96717_VTX_VS_DLY CCI_REG24(0x250) 54 #define MAX96717_VTX_VS_HIGH CCI_REG24(0x253) 55 #define MAX96717_VTX_VS_LOW CCI_REG24(0x256) 56 #define MAX96717_VTX_V2H CCI_REG24(0x259) 57 #define MAX96717_VTX_HS_HIGH CCI_REG16(0x25c) 58 #define MAX96717_VTX_HS_LOW CCI_REG16(0x25e) 59 #define MAX96717_VTX_HS_CNT CCI_REG16(0x260) 60 #define MAX96717_VTX_V2D CCI_REG24(0x262) 61 #define MAX96717_VTX_DE_HIGH CCI_REG16(0x265) 62 #define MAX96717_VTX_DE_LOW CCI_REG16(0x267) 63 #define MAX96717_VTX_DE_CNT CCI_REG16(0x269) 64 #define MAX96717_VTX29 CCI_REG8(0x26b) 65 #define MAX96717_VTX_MODE GENMASK(1, 0) 66 #define MAX96717_VTX_GRAD_INC CCI_REG8(0x26c) 67 #define MAX96717_VTX_CHKB_COLOR_A CCI_REG24(0x26d) 68 #define MAX96717_VTX_CHKB_COLOR_B CCI_REG24(0x270) 69 #define MAX96717_VTX_CHKB_RPT_CNT_A CCI_REG8(0x273) 70 #define MAX96717_VTX_CHKB_RPT_CNT_B CCI_REG8(0x274) 71 #define MAX96717_VTX_CHKB_ALT CCI_REG8(0x275) 72 73 /* GPIO */ 74 #define MAX96717_NUM_GPIO 11 75 #define MAX96717_GPIO_REG_A(gpio) CCI_REG8(0x2be + (gpio) * 3) 76 #define MAX96717_GPIO_OUT BIT(4) 77 #define MAX96717_GPIO_IN BIT(3) 78 #define MAX96717_GPIO_RX_EN BIT(2) 79 #define MAX96717_GPIO_TX_EN BIT(1) 80 #define MAX96717_GPIO_OUT_DIS BIT(0) 81 82 /* FRONTTOP */ 83 /* MAX96717 only have CSI port 'B' */ 84 #define MAX96717_FRONTOP0 CCI_REG8(0x308) 85 #define MAX96717_START_PORT_B BIT(5) 86 87 /* MIPI_RX */ 88 #define MAX96717_MIPI_RX1 CCI_REG8(0x331) 89 #define MAX96717_MIPI_LANES_CNT GENMASK(5, 4) 90 #define MAX96717_MIPI_RX2 CCI_REG8(0x332) /* phy1 Lanes map */ 91 #define MAX96717_PHY2_LANES_MAP GENMASK(7, 4) 92 #define MAX96717_MIPI_RX3 CCI_REG8(0x333) /* phy2 Lanes map */ 93 #define MAX96717_PHY1_LANES_MAP GENMASK(3, 0) 94 #define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */ 95 #define MAX96717_PHY1_LANES_POL GENMASK(6, 4) 96 #define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */ 97 #define MAX96717_PHY2_LANES_POL GENMASK(2, 0) 98 99 /* MIPI_RX_EXT */ 100 #define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383) 101 #define MAX96717_TUN_MODE BIT(7) 102 103 /* REF_VTG */ 104 #define REF_VTG0 CCI_REG8(0x3f0) 105 #define REFGEN_PREDEF_EN BIT(6) 106 #define REFGEN_PREDEF_FREQ_MASK GENMASK(5, 4) 107 #define REFGEN_PREDEF_FREQ_ALT BIT(3) 108 #define REFGEN_RST BIT(1) 109 #define REFGEN_EN BIT(0) 110 111 /* MISC */ 112 #define PIO_SLEW_1 CCI_REG8(0x570) 113 114 enum max96717_vpg_mode { 115 MAX96717_VPG_DISABLED = 0, 116 MAX96717_VPG_CHECKERBOARD = 1, 117 MAX96717_VPG_GRADIENT = 2, 118 }; 119 120 struct max96717_priv { 121 struct i2c_client *client; 122 struct regmap *regmap; 123 struct i2c_mux_core *mux; 124 struct v4l2_mbus_config_mipi_csi2 mipi_csi2; 125 struct v4l2_subdev sd; 126 struct media_pad pads[MAX96717_PORTS]; 127 struct v4l2_ctrl_handler ctrl_handler; 128 struct v4l2_async_notifier notifier; 129 struct v4l2_subdev *source_sd; 130 u16 source_sd_pad; 131 u64 enabled_source_streams; 132 u8 pll_predef_index; 133 struct clk_hw clk_hw; 134 struct gpio_chip gpio_chip; 135 enum max96717_vpg_mode pattern; 136 }; 137 138 static inline struct max96717_priv *sd_to_max96717(struct v4l2_subdev *sd) 139 { 140 return container_of(sd, struct max96717_priv, sd); 141 } 142 143 static inline struct max96717_priv *clk_hw_to_max96717(struct clk_hw *hw) 144 { 145 return container_of(hw, struct max96717_priv, clk_hw); 146 } 147 148 static int max96717_i2c_mux_select(struct i2c_mux_core *mux, u32 chan) 149 { 150 return 0; 151 } 152 153 static int max96717_i2c_mux_init(struct max96717_priv *priv) 154 { 155 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 156 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE, 157 max96717_i2c_mux_select, NULL); 158 if (!priv->mux) 159 return -ENOMEM; 160 161 return i2c_mux_add_adapter(priv->mux, 0, 0); 162 } 163 164 static inline int max96717_start_csi(struct max96717_priv *priv, bool start) 165 { 166 return cci_update_bits(priv->regmap, MAX96717_FRONTOP0, 167 MAX96717_START_PORT_B, 168 start ? MAX96717_START_PORT_B : 0, NULL); 169 } 170 171 static int max96717_apply_patgen_timing(struct max96717_priv *priv, 172 struct v4l2_subdev_state *state) 173 { 174 struct v4l2_mbus_framefmt *fmt = 175 v4l2_subdev_state_get_format(state, MAX96717_PAD_SOURCE); 176 const u32 h_active = fmt->width; 177 const u32 h_fp = 88; 178 const u32 h_sw = 44; 179 const u32 h_bp = 148; 180 u32 h_tot; 181 const u32 v_active = fmt->height; 182 const u32 v_fp = 4; 183 const u32 v_sw = 5; 184 const u32 v_bp = 36; 185 u32 v_tot; 186 int ret = 0; 187 188 h_tot = h_active + h_fp + h_sw + h_bp; 189 v_tot = v_active + v_fp + v_sw + v_bp; 190 191 /* 75 Mhz pixel clock */ 192 cci_update_bits(priv->regmap, MAX96717_VTX1, 193 MAX96717_PATTERN_CLK_FREQ, 0xa, &ret); 194 195 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height, 196 fmt->width); 197 198 cci_write(priv->regmap, MAX96717_VTX_VS_DLY, 0, &ret); 199 cci_write(priv->regmap, MAX96717_VTX_VS_HIGH, v_sw * h_tot, &ret); 200 cci_write(priv->regmap, MAX96717_VTX_VS_LOW, 201 (v_active + v_fp + v_bp) * h_tot, &ret); 202 cci_write(priv->regmap, MAX96717_VTX_HS_HIGH, h_sw, &ret); 203 cci_write(priv->regmap, MAX96717_VTX_HS_LOW, h_active + h_fp + h_bp, 204 &ret); 205 cci_write(priv->regmap, MAX96717_VTX_V2D, 206 h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret); 207 cci_write(priv->regmap, MAX96717_VTX_HS_CNT, v_tot, &ret); 208 cci_write(priv->regmap, MAX96717_VTX_DE_HIGH, h_active, &ret); 209 cci_write(priv->regmap, MAX96717_VTX_DE_LOW, h_fp + h_sw + h_bp, 210 &ret); 211 cci_write(priv->regmap, MAX96717_VTX_DE_CNT, v_active, &ret); 212 /* B G R */ 213 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_A, 0xfecc00, &ret); 214 /* B G R */ 215 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_B, 0x006aa7, &ret); 216 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_A, 0x3c, &ret); 217 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_B, 0x3c, &ret); 218 cci_write(priv->regmap, MAX96717_VTX_CHKB_ALT, 0x3c, &ret); 219 cci_write(priv->regmap, MAX96717_VTX_GRAD_INC, 0x10, &ret); 220 221 return ret; 222 } 223 224 static int max96717_apply_patgen(struct max96717_priv *priv, 225 struct v4l2_subdev_state *state) 226 { 227 unsigned int val; 228 int ret = 0; 229 230 if (priv->pattern) 231 ret = max96717_apply_patgen_timing(priv, state); 232 233 cci_write(priv->regmap, MAX96717_VTX0, priv->pattern ? 0xfb : 0, 234 &ret); 235 236 val = FIELD_PREP(MAX96717_VTX_MODE, priv->pattern); 237 cci_update_bits(priv->regmap, MAX96717_VTX29, MAX96717_VTX_MODE, 238 val, &ret); 239 return ret; 240 } 241 242 static int max96717_s_ctrl(struct v4l2_ctrl *ctrl) 243 { 244 struct max96717_priv *priv = 245 container_of(ctrl->handler, struct max96717_priv, ctrl_handler); 246 int ret; 247 248 switch (ctrl->id) { 249 case V4L2_CID_TEST_PATTERN: 250 if (priv->enabled_source_streams) 251 return -EBUSY; 252 priv->pattern = ctrl->val; 253 break; 254 default: 255 return -EINVAL; 256 } 257 258 /* Use bpp from bpp register */ 259 ret = cci_update_bits(priv->regmap, MAX96717_VIDEO_TX0, 260 MAX96717_VIDEO_AUTO_BPP, 261 priv->pattern ? 0 : MAX96717_VIDEO_AUTO_BPP, 262 NULL); 263 264 /* 265 * Pattern generator doesn't work with tunnel mode. 266 * Needs RGB color format and deserializer tunnel mode must be disabled. 267 */ 268 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX_EXT11, 269 MAX96717_TUN_MODE, 270 priv->pattern ? 0 : MAX96717_TUN_MODE, &ret); 271 } 272 273 static const char * const max96717_test_pattern[] = { 274 "Disabled", 275 "Checkerboard", 276 "Gradient" 277 }; 278 279 static const struct v4l2_ctrl_ops max96717_ctrl_ops = { 280 .s_ctrl = max96717_s_ctrl, 281 }; 282 283 static int max96717_gpiochip_get(struct gpio_chip *gpiochip, 284 unsigned int offset) 285 { 286 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 287 u64 val; 288 int ret; 289 290 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), 291 &val, NULL); 292 if (ret) 293 return ret; 294 295 if (val & MAX96717_GPIO_OUT_DIS) 296 return !!(val & MAX96717_GPIO_IN); 297 else 298 return !!(val & MAX96717_GPIO_OUT); 299 } 300 301 static void max96717_gpiochip_set(struct gpio_chip *gpiochip, 302 unsigned int offset, int value) 303 { 304 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 305 306 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 307 MAX96717_GPIO_OUT, MAX96717_GPIO_OUT, NULL); 308 } 309 310 static int max96717_gpio_get_direction(struct gpio_chip *gpiochip, 311 unsigned int offset) 312 { 313 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 314 u64 val; 315 int ret; 316 317 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), &val, NULL); 318 if (ret < 0) 319 return ret; 320 321 return !!(val & MAX96717_GPIO_OUT_DIS); 322 } 323 324 static int max96717_gpio_direction_out(struct gpio_chip *gpiochip, 325 unsigned int offset, int value) 326 { 327 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 328 329 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 330 MAX96717_GPIO_OUT_DIS | MAX96717_GPIO_OUT, 331 value ? MAX96717_GPIO_OUT : 0, NULL); 332 } 333 334 static int max96717_gpio_direction_in(struct gpio_chip *gpiochip, 335 unsigned int offset) 336 { 337 struct max96717_priv *priv = gpiochip_get_data(gpiochip); 338 339 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset), 340 MAX96717_GPIO_OUT_DIS, MAX96717_GPIO_OUT_DIS, 341 NULL); 342 } 343 344 static int max96717_gpiochip_probe(struct max96717_priv *priv) 345 { 346 struct device *dev = &priv->client->dev; 347 struct gpio_chip *gc = &priv->gpio_chip; 348 int i, ret = 0; 349 350 gc->label = dev_name(dev); 351 gc->parent = dev; 352 gc->owner = THIS_MODULE; 353 gc->ngpio = MAX96717_NUM_GPIO; 354 gc->base = -1; 355 gc->can_sleep = true; 356 gc->get_direction = max96717_gpio_get_direction; 357 gc->direction_input = max96717_gpio_direction_in; 358 gc->direction_output = max96717_gpio_direction_out; 359 gc->set = max96717_gpiochip_set; 360 gc->get = max96717_gpiochip_get; 361 gc->of_gpio_n_cells = 2; 362 363 /* Disable GPIO forwarding */ 364 for (i = 0; i < gc->ngpio; i++) 365 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(i), 366 MAX96717_GPIO_RX_EN | MAX96717_GPIO_TX_EN, 367 0, &ret); 368 369 if (ret) 370 return ret; 371 372 ret = devm_gpiochip_add_data(dev, gc, priv); 373 if (ret) { 374 dev_err(dev, "Unable to create gpio_chip\n"); 375 return ret; 376 } 377 378 return 0; 379 } 380 381 static int _max96717_set_routing(struct v4l2_subdev *sd, 382 struct v4l2_subdev_state *state, 383 struct v4l2_subdev_krouting *routing) 384 { 385 static const struct v4l2_mbus_framefmt format = { 386 .width = 1280, 387 .height = 1080, 388 .code = MEDIA_BUS_FMT_Y8_1X8, 389 .field = V4L2_FIELD_NONE, 390 }; 391 int ret; 392 393 ret = v4l2_subdev_routing_validate(sd, routing, 394 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 395 if (ret) 396 return ret; 397 398 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 399 if (ret) 400 return ret; 401 402 return 0; 403 } 404 405 static int max96717_set_routing(struct v4l2_subdev *sd, 406 struct v4l2_subdev_state *state, 407 enum v4l2_subdev_format_whence which, 408 struct v4l2_subdev_krouting *routing) 409 { 410 struct max96717_priv *priv = sd_to_max96717(sd); 411 412 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 413 return -EBUSY; 414 415 return _max96717_set_routing(sd, state, routing); 416 } 417 418 static int max96717_set_fmt(struct v4l2_subdev *sd, 419 struct v4l2_subdev_state *state, 420 struct v4l2_subdev_format *format) 421 { 422 struct max96717_priv *priv = sd_to_max96717(sd); 423 struct v4l2_mbus_framefmt *fmt; 424 u64 stream_source_mask; 425 426 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 427 priv->enabled_source_streams) 428 return -EBUSY; 429 430 /* No transcoding, source and sink formats must match. */ 431 if (format->pad == MAX96717_PAD_SOURCE) 432 return v4l2_subdev_get_fmt(sd, state, format); 433 434 /* Set sink format */ 435 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 436 if (!fmt) 437 return -EINVAL; 438 439 *fmt = format->format; 440 441 /* Propagate to source format */ 442 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 443 format->stream); 444 if (!fmt) 445 return -EINVAL; 446 *fmt = format->format; 447 448 stream_source_mask = BIT(format->stream); 449 450 return v4l2_subdev_state_xlate_streams(state, MAX96717_PAD_SOURCE, 451 MAX96717_PAD_SINK, 452 &stream_source_mask); 453 } 454 455 static int max96717_init_state(struct v4l2_subdev *sd, 456 struct v4l2_subdev_state *state) 457 { 458 struct v4l2_subdev_route routes[] = { 459 { 460 .sink_pad = MAX96717_PAD_SINK, 461 .sink_stream = 0, 462 .source_pad = MAX96717_PAD_SOURCE, 463 .source_stream = 0, 464 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 465 }, 466 }; 467 struct v4l2_subdev_krouting routing = { 468 .num_routes = ARRAY_SIZE(routes), 469 .routes = routes, 470 }; 471 472 return _max96717_set_routing(sd, state, &routing); 473 } 474 475 static bool max96717_pipe_pclkdet(struct max96717_priv *priv) 476 { 477 u64 val = 0; 478 479 cci_read(priv->regmap, MAX96717_VIDEO_TX2, &val, NULL); 480 481 return val & MAX96717_VIDEO_PCLKDET; 482 } 483 484 static int max96717_log_status(struct v4l2_subdev *sd) 485 { 486 struct max96717_priv *priv = sd_to_max96717(sd); 487 struct device *dev = &priv->client->dev; 488 489 dev_info(dev, "Serializer: max96717\n"); 490 dev_info(dev, "Pipe: pclkdet:%d\n", max96717_pipe_pclkdet(priv)); 491 492 return 0; 493 } 494 495 static int max96717_enable_streams(struct v4l2_subdev *sd, 496 struct v4l2_subdev_state *state, u32 pad, 497 u64 streams_mask) 498 { 499 struct max96717_priv *priv = sd_to_max96717(sd); 500 u64 sink_streams; 501 int ret; 502 503 if (!priv->enabled_source_streams) 504 max96717_start_csi(priv, true); 505 506 ret = max96717_apply_patgen(priv, state); 507 if (ret) 508 goto stop_csi; 509 510 if (!priv->pattern) { 511 sink_streams = 512 v4l2_subdev_state_xlate_streams(state, 513 MAX96717_PAD_SOURCE, 514 MAX96717_PAD_SINK, 515 &streams_mask); 516 517 ret = v4l2_subdev_enable_streams(priv->source_sd, 518 priv->source_sd_pad, 519 sink_streams); 520 if (ret) 521 goto stop_csi; 522 } 523 524 priv->enabled_source_streams |= streams_mask; 525 526 return 0; 527 528 stop_csi: 529 if (!priv->enabled_source_streams) 530 max96717_start_csi(priv, false); 531 532 return ret; 533 } 534 535 static int max96717_disable_streams(struct v4l2_subdev *sd, 536 struct v4l2_subdev_state *state, u32 pad, 537 u64 streams_mask) 538 { 539 struct max96717_priv *priv = sd_to_max96717(sd); 540 u64 sink_streams; 541 542 /* 543 * Stop the CSI receiver first then the source, 544 * otherwise the device may become unresponsive 545 * while holding the I2C bus low. 546 */ 547 priv->enabled_source_streams &= ~streams_mask; 548 if (!priv->enabled_source_streams) 549 max96717_start_csi(priv, false); 550 551 if (!priv->pattern) { 552 int ret; 553 554 sink_streams = 555 v4l2_subdev_state_xlate_streams(state, 556 MAX96717_PAD_SOURCE, 557 MAX96717_PAD_SINK, 558 &streams_mask); 559 560 ret = v4l2_subdev_disable_streams(priv->source_sd, 561 priv->source_sd_pad, 562 sink_streams); 563 if (ret) 564 return ret; 565 } 566 567 return 0; 568 } 569 570 static const struct v4l2_subdev_pad_ops max96717_pad_ops = { 571 .enable_streams = max96717_enable_streams, 572 .disable_streams = max96717_disable_streams, 573 .set_routing = max96717_set_routing, 574 .get_fmt = v4l2_subdev_get_fmt, 575 .set_fmt = max96717_set_fmt, 576 }; 577 578 static const struct v4l2_subdev_core_ops max96717_subdev_core_ops = { 579 .log_status = max96717_log_status, 580 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 581 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 582 }; 583 584 static const struct v4l2_subdev_internal_ops max96717_internal_ops = { 585 .init_state = max96717_init_state, 586 }; 587 588 static const struct v4l2_subdev_ops max96717_subdev_ops = { 589 .core = &max96717_subdev_core_ops, 590 .pad = &max96717_pad_ops, 591 }; 592 593 static const struct media_entity_operations max96717_entity_ops = { 594 .link_validate = v4l2_subdev_link_validate, 595 }; 596 597 static int max96717_notify_bound(struct v4l2_async_notifier *notifier, 598 struct v4l2_subdev *source_subdev, 599 struct v4l2_async_connection *asd) 600 { 601 struct max96717_priv *priv = sd_to_max96717(notifier->sd); 602 struct device *dev = &priv->client->dev; 603 int ret; 604 605 ret = media_entity_get_fwnode_pad(&source_subdev->entity, 606 source_subdev->fwnode, 607 MEDIA_PAD_FL_SOURCE); 608 if (ret < 0) { 609 dev_err(dev, "Failed to find pad for %s\n", 610 source_subdev->name); 611 return ret; 612 } 613 614 priv->source_sd = source_subdev; 615 priv->source_sd_pad = ret; 616 617 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad, 618 &priv->sd.entity, 0, 619 MEDIA_LNK_FL_ENABLED | 620 MEDIA_LNK_FL_IMMUTABLE); 621 if (ret) { 622 dev_err(dev, "Unable to link %s:%u -> %s:0\n", 623 source_subdev->name, priv->source_sd_pad, 624 priv->sd.name); 625 return ret; 626 } 627 628 return 0; 629 } 630 631 static const struct v4l2_async_notifier_operations max96717_notify_ops = { 632 .bound = max96717_notify_bound, 633 }; 634 635 static int max96717_v4l2_notifier_register(struct max96717_priv *priv) 636 { 637 struct device *dev = &priv->client->dev; 638 struct v4l2_async_connection *asd; 639 struct fwnode_handle *ep_fwnode; 640 int ret; 641 642 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 643 MAX96717_PAD_SINK, 0, 0); 644 if (!ep_fwnode) { 645 dev_err(dev, "No graph endpoint\n"); 646 return -ENODEV; 647 } 648 649 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 650 651 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode, 652 struct v4l2_async_connection); 653 654 fwnode_handle_put(ep_fwnode); 655 656 if (IS_ERR(asd)) { 657 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd)); 658 v4l2_async_nf_cleanup(&priv->notifier); 659 return PTR_ERR(asd); 660 } 661 662 priv->notifier.ops = &max96717_notify_ops; 663 664 ret = v4l2_async_nf_register(&priv->notifier); 665 if (ret) { 666 dev_err(dev, "Failed to register subdev_notifier"); 667 v4l2_async_nf_cleanup(&priv->notifier); 668 return ret; 669 } 670 671 return 0; 672 } 673 674 static int max96717_subdev_init(struct max96717_priv *priv) 675 { 676 struct device *dev = &priv->client->dev; 677 int ret; 678 679 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96717_subdev_ops); 680 priv->sd.internal_ops = &max96717_internal_ops; 681 682 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1); 683 priv->sd.ctrl_handler = &priv->ctrl_handler; 684 685 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, 686 &max96717_ctrl_ops, 687 V4L2_CID_TEST_PATTERN, 688 ARRAY_SIZE(max96717_test_pattern) - 1, 689 0, 0, max96717_test_pattern); 690 if (priv->ctrl_handler.error) { 691 ret = priv->ctrl_handler.error; 692 goto err_free_ctrl; 693 } 694 695 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 696 V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS; 697 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 698 priv->sd.entity.ops = &max96717_entity_ops; 699 700 priv->pads[MAX96717_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 701 priv->pads[MAX96717_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 702 703 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads); 704 if (ret) { 705 dev_err_probe(dev, ret, "Failed to init pads\n"); 706 goto err_free_ctrl; 707 } 708 709 ret = v4l2_subdev_init_finalize(&priv->sd); 710 if (ret) { 711 dev_err_probe(dev, ret, 712 "v4l2 subdev init finalized failed\n"); 713 goto err_entity_cleanup; 714 } 715 ret = max96717_v4l2_notifier_register(priv); 716 if (ret) { 717 dev_err_probe(dev, ret, 718 "v4l2 subdev notifier register failed\n"); 719 goto err_free_state; 720 } 721 722 ret = v4l2_async_register_subdev(&priv->sd); 723 if (ret) { 724 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n"); 725 goto err_unreg_notif; 726 } 727 728 return 0; 729 730 err_unreg_notif: 731 v4l2_async_nf_unregister(&priv->notifier); 732 v4l2_async_nf_cleanup(&priv->notifier); 733 err_free_state: 734 v4l2_subdev_cleanup(&priv->sd); 735 err_entity_cleanup: 736 media_entity_cleanup(&priv->sd.entity); 737 err_free_ctrl: 738 v4l2_ctrl_handler_free(&priv->ctrl_handler); 739 740 return ret; 741 } 742 743 static void max96717_subdev_uninit(struct max96717_priv *priv) 744 { 745 v4l2_async_unregister_subdev(&priv->sd); 746 v4l2_async_nf_unregister(&priv->notifier); 747 v4l2_async_nf_cleanup(&priv->notifier); 748 v4l2_subdev_cleanup(&priv->sd); 749 media_entity_cleanup(&priv->sd.entity); 750 v4l2_ctrl_handler_free(&priv->ctrl_handler); 751 } 752 753 struct max96717_pll_predef_freq { 754 unsigned long freq; 755 bool is_alt; 756 u8 val; 757 }; 758 759 static const struct max96717_pll_predef_freq max96717_predef_freqs[] = { 760 { 13500000, true, 0 }, { 19200000, false, 0 }, 761 { 24000000, true, 1 }, { 27000000, false, 1 }, 762 { 37125000, false, 2 }, { 74250000, false, 3 }, 763 }; 764 765 static unsigned long 766 max96717_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 767 { 768 struct max96717_priv *priv = clk_hw_to_max96717(hw); 769 770 return max96717_predef_freqs[priv->pll_predef_index].freq; 771 } 772 773 static unsigned int max96717_clk_find_best_index(struct max96717_priv *priv, 774 unsigned long rate) 775 { 776 unsigned int i, idx = 0; 777 unsigned long diff_new, diff_old = U32_MAX; 778 779 for (i = 0; i < ARRAY_SIZE(max96717_predef_freqs); i++) { 780 diff_new = abs(rate - max96717_predef_freqs[i].freq); 781 if (diff_new < diff_old) { 782 diff_old = diff_new; 783 idx = i; 784 } 785 } 786 787 return idx; 788 } 789 790 static long max96717_clk_round_rate(struct clk_hw *hw, unsigned long rate, 791 unsigned long *parent_rate) 792 { 793 struct max96717_priv *priv = clk_hw_to_max96717(hw); 794 struct device *dev = &priv->client->dev; 795 unsigned int idx; 796 797 idx = max96717_clk_find_best_index(priv, rate); 798 799 if (rate != max96717_predef_freqs[idx].freq) { 800 dev_warn(dev, "Request CLK freq:%lu, found CLK freq:%lu\n", 801 rate, max96717_predef_freqs[idx].freq); 802 } 803 804 return max96717_predef_freqs[idx].freq; 805 } 806 807 static int max96717_clk_set_rate(struct clk_hw *hw, unsigned long rate, 808 unsigned long parent_rate) 809 { 810 struct max96717_priv *priv = clk_hw_to_max96717(hw); 811 unsigned int val, idx; 812 int ret = 0; 813 814 idx = max96717_clk_find_best_index(priv, rate); 815 816 val = FIELD_PREP(REFGEN_PREDEF_FREQ_MASK, 817 max96717_predef_freqs[idx].val); 818 819 if (max96717_predef_freqs[idx].is_alt) 820 val |= REFGEN_PREDEF_FREQ_ALT; 821 822 val |= REFGEN_RST | REFGEN_PREDEF_EN; 823 824 cci_write(priv->regmap, REF_VTG0, val, &ret); 825 cci_update_bits(priv->regmap, REF_VTG0, REFGEN_RST | REFGEN_EN, 826 REFGEN_EN, &ret); 827 if (ret) 828 return ret; 829 830 priv->pll_predef_index = idx; 831 832 return 0; 833 } 834 835 static int max96717_clk_prepare(struct clk_hw *hw) 836 { 837 struct max96717_priv *priv = clk_hw_to_max96717(hw); 838 839 return cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 840 RCLKEN, NULL); 841 } 842 843 static void max96717_clk_unprepare(struct clk_hw *hw) 844 { 845 struct max96717_priv *priv = clk_hw_to_max96717(hw); 846 847 cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 0, NULL); 848 } 849 850 static const struct clk_ops max96717_clk_ops = { 851 .prepare = max96717_clk_prepare, 852 .unprepare = max96717_clk_unprepare, 853 .set_rate = max96717_clk_set_rate, 854 .recalc_rate = max96717_clk_recalc_rate, 855 .round_rate = max96717_clk_round_rate, 856 }; 857 858 static int max96717_register_clkout(struct max96717_priv *priv) 859 { 860 struct device *dev = &priv->client->dev; 861 struct clk_init_data init = { .ops = &max96717_clk_ops }; 862 int ret; 863 864 init.name = kasprintf(GFP_KERNEL, "max96717.%s.clk_out", dev_name(dev)); 865 if (!init.name) 866 return -ENOMEM; 867 868 /* RCLKSEL Reference PLL output */ 869 ret = cci_update_bits(priv->regmap, MAX96717_REG3, MAX96717_RCLKSEL, 870 MAX96717_RCLKSEL, NULL); 871 /* MFP4 fastest slew rate */ 872 cci_update_bits(priv->regmap, PIO_SLEW_1, BIT(5) | BIT(4), 0, &ret); 873 if (ret) 874 goto free_init_name; 875 876 priv->clk_hw.init = &init; 877 878 /* Initialize to 24 MHz */ 879 ret = max96717_clk_set_rate(&priv->clk_hw, 880 MAX96717_DEFAULT_CLKOUT_RATE, 0); 881 if (ret < 0) 882 goto free_init_name; 883 884 ret = devm_clk_hw_register(dev, &priv->clk_hw); 885 kfree(init.name); 886 if (ret) 887 return dev_err_probe(dev, ret, "Cannot register clock HW\n"); 888 889 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 890 &priv->clk_hw); 891 if (ret) 892 return dev_err_probe(dev, ret, 893 "Cannot add OF clock provider\n"); 894 895 return 0; 896 897 free_init_name: 898 kfree(init.name); 899 return ret; 900 } 901 902 static int max96717_init_csi_lanes(struct max96717_priv *priv) 903 { 904 struct v4l2_mbus_config_mipi_csi2 *mipi = &priv->mipi_csi2; 905 unsigned long lanes_used = 0; 906 unsigned int nlanes, lane, val = 0; 907 int ret; 908 909 nlanes = mipi->num_data_lanes; 910 911 ret = cci_update_bits(priv->regmap, MAX96717_MIPI_RX1, 912 MAX96717_MIPI_LANES_CNT, 913 FIELD_PREP(MAX96717_MIPI_LANES_CNT, 914 nlanes - 1), NULL); 915 916 /* lanes polarity */ 917 for (lane = 0; lane < nlanes + 1; lane++) { 918 if (!mipi->lane_polarities[lane]) 919 continue; 920 /* Clock lane */ 921 if (lane == 0) 922 val |= BIT(2); 923 else if (lane < 3) 924 val |= BIT(lane - 1); 925 else 926 val |= BIT(lane); 927 } 928 929 cci_update_bits(priv->regmap, MAX96717_MIPI_RX5, 930 MAX96717_PHY2_LANES_POL, 931 FIELD_PREP(MAX96717_PHY2_LANES_POL, val), &ret); 932 933 cci_update_bits(priv->regmap, MAX96717_MIPI_RX4, 934 MAX96717_PHY1_LANES_POL, 935 FIELD_PREP(MAX96717_PHY1_LANES_POL, 936 val >> 3), &ret); 937 /* lanes mapping */ 938 for (lane = 0, val = 0; lane < nlanes; lane++) { 939 val |= (mipi->data_lanes[lane] - 1) << (lane * 2); 940 lanes_used |= BIT(mipi->data_lanes[lane] - 1); 941 } 942 943 /* 944 * Unused lanes need to be mapped as well to not have 945 * the same lanes mapped twice. 946 */ 947 for (; lane < MAX96717_CSI_NLANES; lane++) { 948 unsigned int idx = find_first_zero_bit(&lanes_used, 949 MAX96717_CSI_NLANES); 950 951 val |= idx << (lane * 2); 952 lanes_used |= BIT(idx); 953 } 954 955 cci_update_bits(priv->regmap, MAX96717_MIPI_RX3, 956 MAX96717_PHY1_LANES_MAP, 957 FIELD_PREP(MAX96717_PHY1_LANES_MAP, val), &ret); 958 959 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX2, 960 MAX96717_PHY2_LANES_MAP, 961 FIELD_PREP(MAX96717_PHY2_LANES_MAP, val >> 4), 962 &ret); 963 } 964 965 static int max96717_hw_init(struct max96717_priv *priv) 966 { 967 struct device *dev = &priv->client->dev; 968 u64 dev_id, val; 969 int ret; 970 971 ret = cci_read(priv->regmap, MAX96717_DEV_ID, &dev_id, NULL); 972 if (ret) 973 return dev_err_probe(dev, ret, 974 "Fail to read the device id\n"); 975 976 if (dev_id != MAX96717_DEVICE_ID && dev_id != MAX96717F_DEVICE_ID) 977 return dev_err_probe(dev, -EOPNOTSUPP, 978 "Unsupported device id got %x\n", (u8)dev_id); 979 980 ret = cci_read(priv->regmap, MAX96717_DEV_REV, &val, NULL); 981 if (ret) 982 return dev_err_probe(dev, ret, 983 "Fail to read device revision"); 984 985 dev_dbg(dev, "Found %x (rev %lx)\n", (u8)dev_id, 986 (u8)val & MAX96717_DEV_REV_MASK); 987 988 ret = cci_read(priv->regmap, MAX96717_MIPI_RX_EXT11, &val, NULL); 989 if (ret) 990 return dev_err_probe(dev, ret, 991 "Fail to read mipi rx extension"); 992 993 if (!(val & MAX96717_TUN_MODE)) 994 return dev_err_probe(dev, -EOPNOTSUPP, 995 "Only supporting tunnel mode"); 996 997 return max96717_init_csi_lanes(priv); 998 } 999 1000 static int max96717_parse_dt(struct max96717_priv *priv) 1001 { 1002 struct device *dev = &priv->client->dev; 1003 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 1004 struct fwnode_handle *ep_fwnode; 1005 unsigned char num_data_lanes; 1006 int ret; 1007 1008 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 1009 MAX96717_PAD_SINK, 0, 0); 1010 if (!ep_fwnode) 1011 return dev_err_probe(dev, -ENOENT, "no endpoint found\n"); 1012 1013 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep); 1014 1015 fwnode_handle_put(ep_fwnode); 1016 1017 if (ret < 0) 1018 return dev_err_probe(dev, ret, "Failed to parse sink endpoint"); 1019 1020 num_data_lanes = vep.bus.mipi_csi2.num_data_lanes; 1021 if (num_data_lanes < 1 || num_data_lanes > MAX96717_CSI_NLANES) 1022 return dev_err_probe(dev, -EINVAL, 1023 "Invalid data lanes must be 1 to 4\n"); 1024 1025 priv->mipi_csi2 = vep.bus.mipi_csi2; 1026 1027 return 0; 1028 } 1029 1030 static int max96717_probe(struct i2c_client *client) 1031 { 1032 struct device *dev = &client->dev; 1033 struct max96717_priv *priv; 1034 int ret; 1035 1036 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1037 if (!priv) 1038 return -ENOMEM; 1039 1040 priv->client = client; 1041 priv->regmap = devm_cci_regmap_init_i2c(client, 16); 1042 if (IS_ERR(priv->regmap)) { 1043 ret = PTR_ERR(priv->regmap); 1044 return dev_err_probe(dev, ret, "Failed to init regmap\n"); 1045 } 1046 1047 ret = max96717_parse_dt(priv); 1048 if (ret) 1049 return dev_err_probe(dev, ret, "Failed to parse the dt\n"); 1050 1051 ret = max96717_hw_init(priv); 1052 if (ret) 1053 return dev_err_probe(dev, ret, 1054 "Failed to initialize the hardware\n"); 1055 1056 ret = max96717_gpiochip_probe(priv); 1057 if (ret) 1058 return dev_err_probe(&client->dev, ret, 1059 "Failed to init gpiochip\n"); 1060 1061 ret = max96717_register_clkout(priv); 1062 if (ret) 1063 return dev_err_probe(dev, ret, "Failed to register clkout\n"); 1064 1065 ret = max96717_subdev_init(priv); 1066 if (ret) 1067 return dev_err_probe(dev, ret, 1068 "Failed to initialize v4l2 subdev\n"); 1069 1070 ret = max96717_i2c_mux_init(priv); 1071 if (ret) { 1072 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n"); 1073 max96717_subdev_uninit(priv); 1074 } 1075 1076 return ret; 1077 } 1078 1079 static void max96717_remove(struct i2c_client *client) 1080 { 1081 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1082 struct max96717_priv *priv = sd_to_max96717(sd); 1083 1084 max96717_subdev_uninit(priv); 1085 i2c_mux_del_adapters(priv->mux); 1086 } 1087 1088 static const struct of_device_id max96717_of_ids[] = { 1089 { .compatible = "maxim,max96717f" }, 1090 { } 1091 }; 1092 MODULE_DEVICE_TABLE(of, max96717_of_ids); 1093 1094 static struct i2c_driver max96717_i2c_driver = { 1095 .driver = { 1096 .name = "max96717", 1097 .of_match_table = max96717_of_ids, 1098 }, 1099 .probe = max96717_probe, 1100 .remove = max96717_remove, 1101 }; 1102 1103 module_i2c_driver(max96717_i2c_driver); 1104 1105 MODULE_DESCRIPTION("Maxim GMSL2 MAX96717 Serializer Driver"); 1106 MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>"); 1107 MODULE_LICENSE("GPL"); 1108