drm/amd/display: Fix CRC engine 1 enable/disable on DCN3.1.2+[Why]Multi-ROI CRC uses OTG_CRC1_EN for the second engine, but the driveronly toggled OTG_CRC_EN and cleared the whole OTG_CRC_CNTL re
drm/amd/display: Fix CRC engine 1 enable/disable on DCN3.1.2+[Why]Multi-ROI CRC uses OTG_CRC1_EN for the second engine, but the driveronly toggled OTG_CRC_EN and cleared the whole OTG_CRC_CNTL register ondisable.[How]Program engine 1 via OTG_CRC1_EN where supported, disable eachengine independently by crc_eng_inst, and add the missing mask onrelevant DCN ASICs.Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>Signed-off-by: Roman Li <roman.li@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drm/amd/display: Enable DCN6 sources compilation- Add hooks in various entry points to perform hw/sw init for DCN6 asic- Add dependent changes needed to enable DCN6 asic- Update the Makefiles so
drm/amd/display: Enable DCN6 sources compilation- Add hooks in various entry points to perform hw/sw init for DCN6 asic- Add dependent changes needed to enable DCN6 asic- Update the Makefiles so that DCN6 related newly added sources are compiledSigned-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Signed-off-by: Roman Li <Roman.Li@amd.com>Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add DCN42B code to DC[Why & How]Add DCN42B code to DCReviewed-by: Harry Wentland <harry.wentland@amd.com>Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>Signed-off-by
drm/amd/display: Add DCN42B code to DC[Why & How]Add DCN42B code to DCReviewed-by: Harry Wentland <harry.wentland@amd.com>Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>Signed-off-by: Ray Wu <ray.wu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Enable additional wait for pipe pending checks[why]In cases where there are two FULL updates within the same display frame,it's possible for some blocks to be programmed a second
drm/amd/display: Enable additional wait for pipe pending checks[why]In cases where there are two FULL updates within the same display frame,it's possible for some blocks to be programmed a second time without havingbeen latched completely from the first programming.DCN 3.5 and up already work around this with additional validation checksfor frame count and defer as needed via fsleep.[how]Enabled existing pipe checks generically for all DCN versions to avoid HWprogramming hazards.Also removed redundant max_frame_count which can be determined by theregister mask and shift.Reviewed-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove SYMCLK F and G values from link encoder and MANUAL_FLOW_CONTROL from optc[WHY]Definitions were removed by HW from new headers.Reviewed-by: Charlene Liu <charlene.liu@amd.
drm/amd/display: Remove SYMCLK F and G values from link encoder and MANUAL_FLOW_CONTROL from optc[WHY]Definitions were removed by HW from new headers.Reviewed-by: Charlene Liu <charlene.liu@amd.com>Signed-off-by: Andrew Lichmanov <Andrew.Lichmanov@amd.com>Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Sync dcn42 with DC 3.2.373This patch provides a bulk merge to align driversupport for DCN42 with Display Core version 3.2.373.It includes upgrade for:- clk_mgr- dml2/dml21- o
drm/amd/display: Sync dcn42 with DC 3.2.373This patch provides a bulk merge to align driversupport for DCN42 with Display Core version 3.2.373.It includes upgrade for:- clk_mgr- dml2/dml21- optc- hubp- mpc- optc- hwseqAcked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Signed-off-by: Roman Li <Roman.Li@amd.com>Signed-off-by: Alex Hung <alex.hung@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add dcn42 DC resourcesDisplay Core resources for DCN 4.2:- CLK_MGR- DCCG- DIO- DPP- GPIO- HPO- HUBBUB- HUBP- HWSS- IRQ- MMHUBBUB- MPC- OPTC- PGSigned-off-by: Roman
drm/amd/display: Add dcn42 DC resourcesDisplay Core resources for DCN 4.2:- CLK_MGR- DCCG- DIO- DPP- GPIO- HPO- HUBBUB- HUBP- HWSS- IRQ- MMHUBBUB- MPC- OPTC- PGSigned-off-by: Roman Li <Roman.Li@amd.com>Acked-by: Harry Wentland <harry.wentland@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>