1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 34 #include "amdgpu.h" 35 #include "atom.h" 36 #include "amdgpu_trace.h" 37 38 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 39 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 40 41 /* 42 * IB 43 * IBs (Indirect Buffers) and areas of GPU accessible memory where 44 * commands are stored. You can put a pointer to the IB in the 45 * command ring and the hw will fetch the commands from the IB 46 * and execute them. Generally userspace acceleration drivers 47 * produce command buffers which are send to the kernel and 48 * put in IBs for execution by the requested ring. 49 */ 50 51 /** 52 * amdgpu_ib_get - request an IB (Indirect Buffer) 53 * 54 * @adev: amdgpu_device pointer 55 * @vm: amdgpu_vm pointer 56 * @size: requested IB size 57 * @pool_type: IB pool type (delayed, immediate, direct) 58 * @ib: IB object returned 59 * 60 * Request an IB (all asics). IBs are allocated using the 61 * suballocator. 62 * Returns 0 on success, error on failure. 63 */ 64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 65 unsigned int size, enum amdgpu_ib_pool_type pool_type, 66 struct amdgpu_ib *ib) 67 { 68 int r; 69 70 if (size) { 71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 72 &ib->sa_bo, size); 73 if (r) { 74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 75 return r; 76 } 77 78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 79 /* flush the cache before commit the IB */ 80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; 81 82 if (!vm) 83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 84 } 85 86 return 0; 87 } 88 89 /** 90 * amdgpu_ib_free - free an IB (Indirect Buffer) 91 * 92 * @ib: IB object to free 93 * @f: the fence SA bo need wait on for the ib alloation 94 * 95 * Free an IB (all asics). 96 */ 97 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f) 98 { 99 amdgpu_sa_bo_free(&ib->sa_bo, f); 100 } 101 102 /** 103 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 104 * 105 * @ring: ring index the IB is associated with 106 * @num_ibs: number of IBs to schedule 107 * @ibs: IB objects to schedule 108 * @job: job to schedule 109 * @f: fence created during this submission 110 * 111 * Schedule an IB on the associated ring (all asics). 112 * Returns 0 on success, error on failure. 113 * 114 * On SI, there are two parallel engines fed from the primary ring, 115 * the CE (Constant Engine) and the DE (Drawing Engine). Since 116 * resource descriptors have moved to memory, the CE allows you to 117 * prime the caches while the DE is updating register state so that 118 * the resource descriptors will be already in cache when the draw is 119 * processed. To accomplish this, the userspace driver submits two 120 * IBs, one for the CE and one for the DE. If there is a CE IB (called 121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 122 * to SI there was just a DE IB. 123 */ 124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 125 struct amdgpu_ib *ibs, struct amdgpu_job *job, 126 struct dma_fence **f) 127 { 128 struct amdgpu_device *adev = ring->adev; 129 struct amdgpu_ib *ib = &ibs[0]; 130 struct dma_fence *tmp = NULL; 131 struct amdgpu_fence *af; 132 struct amdgpu_fence *vm_af; 133 bool need_ctx_switch; 134 struct amdgpu_vm *vm; 135 uint64_t fence_ctx; 136 uint32_t status = 0, alloc_size; 137 unsigned int fence_flags = 0; 138 bool secure, init_shadow; 139 u64 shadow_va, csa_va, gds_va; 140 int vmid = AMDGPU_JOB_GET_VMID(job); 141 bool need_pipe_sync = false; 142 unsigned int cond_exec; 143 unsigned int i; 144 int r = 0; 145 146 if (num_ibs == 0) 147 return -EINVAL; 148 149 /* ring tests don't use a job */ 150 if (job) { 151 vm = job->vm; 152 fence_ctx = job->base.s_fence ? 153 job->base.s_fence->finished.context : 0; 154 shadow_va = job->shadow_va; 155 csa_va = job->csa_va; 156 gds_va = job->gds_va; 157 init_shadow = job->init_shadow; 158 af = job->hw_fence; 159 /* Save the context of the job for reset handling. 160 * The driver needs this so it can skip the ring 161 * contents for guilty contexts. 162 */ 163 af->context = fence_ctx; 164 /* the vm fence is also part of the job's context */ 165 job->hw_vm_fence->context = fence_ctx; 166 } else { 167 vm = NULL; 168 fence_ctx = 0; 169 shadow_va = 0; 170 csa_va = 0; 171 gds_va = 0; 172 init_shadow = false; 173 af = kzalloc_obj(*af, GFP_ATOMIC); 174 if (!af) 175 return -ENOMEM; 176 } 177 178 if (!ring->sched.ready) { 179 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 180 r = -EINVAL; 181 goto free_fence; 182 } 183 184 if (vm && !job->vmid) { 185 dev_err(adev->dev, "VM IB without ID\n"); 186 r = -EINVAL; 187 goto free_fence; 188 } 189 190 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 191 (!ring->funcs->secure_submission_supported)) { 192 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); 193 r = -EINVAL; 194 goto free_fence; 195 } 196 197 alloc_size = ring->funcs->emit_frame_size + num_ibs * 198 ring->funcs->emit_ib_size; 199 200 r = amdgpu_ring_alloc(ring, alloc_size); 201 if (r) { 202 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 203 goto free_fence; 204 } 205 206 need_ctx_switch = ring->current_ctx != fence_ctx; 207 if (ring->funcs->emit_pipeline_sync && job && 208 ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) || 209 need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) { 210 211 need_pipe_sync = true; 212 213 if (tmp) 214 trace_amdgpu_ib_pipe_sync(job, tmp); 215 216 dma_fence_put(tmp); 217 } 218 219 if (job) { 220 vm_af = job->hw_vm_fence; 221 /* VM sequence */ 222 vm_af->ib_wptr = ring->wptr; 223 amdgpu_vm_flush(ring, job, need_pipe_sync); 224 vm_af->ib_dw_size = 225 amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr); 226 } 227 228 /* IB sequence */ 229 af->ib_wptr = ring->wptr; 230 amdgpu_ring_ib_begin(ring); 231 232 if (ring->funcs->insert_start) 233 ring->funcs->insert_start(ring); 234 235 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 236 ring->funcs->emit_mem_sync(ring); 237 238 if (ring->funcs->emit_wave_limit && 239 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 240 ring->funcs->emit_wave_limit(ring, true); 241 242 if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) 243 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, 244 init_shadow, vmid); 245 246 if (ring->funcs->init_cond_exec) 247 cond_exec = amdgpu_ring_init_cond_exec(ring, 248 ring->cond_exe_gpu_addr); 249 250 /* Skip the IB for guilty contexts */ 251 af->skip_ib_dw_start_offset = 252 amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); 253 amdgpu_device_flush_hdp(adev, ring); 254 255 if (need_ctx_switch) 256 status |= AMDGPU_HAVE_CTX_SWITCH; 257 258 if (job && ring->funcs->emit_cntxcntl) { 259 status |= job->preamble_status; 260 status |= job->preemption_status; 261 amdgpu_ring_emit_cntxcntl(ring, status); 262 } 263 264 /* Setup initial TMZiness and send it off. 265 */ 266 secure = false; 267 if (job && ring->funcs->emit_frame_cntl) { 268 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 269 amdgpu_ring_emit_frame_cntl(ring, true, secure); 270 } 271 272 for (i = 0; i < num_ibs; ++i) { 273 ib = &ibs[i]; 274 275 if (job && ring->funcs->emit_frame_cntl) { 276 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 277 amdgpu_ring_emit_frame_cntl(ring, false, secure); 278 secure = !secure; 279 amdgpu_ring_emit_frame_cntl(ring, true, secure); 280 } 281 } 282 283 amdgpu_ring_emit_ib(ring, job, ib, status); 284 status &= ~AMDGPU_HAVE_CTX_SWITCH; 285 } 286 287 if (job && ring->funcs->emit_frame_cntl) 288 amdgpu_ring_emit_frame_cntl(ring, false, secure); 289 290 amdgpu_device_invalidate_hdp(adev, ring); 291 /* Skip the IB for guilty contexts */ 292 af->skip_ib_dw_end_offset = 293 amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); 294 295 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 296 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 297 298 /* wrap the last IB with fence */ 299 if (job && job->uf_addr) { 300 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 301 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 302 } 303 304 if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec && 305 adev->gfx.cp_gfx_shadow) { 306 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); 307 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); 308 } 309 310 amdgpu_fence_emit(ring, af, fence_flags); 311 *f = &af->base; 312 /* get a ref for the job */ 313 if (job) 314 dma_fence_get(*f); 315 316 if (ring->funcs->insert_end) 317 ring->funcs->insert_end(ring); 318 319 amdgpu_ring_patch_cond_exec(ring, cond_exec); 320 321 ring->current_ctx = fence_ctx; 322 if (job && ring->funcs->emit_switch_buffer) 323 amdgpu_ring_emit_switch_buffer(ring); 324 325 if (ring->funcs->emit_wave_limit && 326 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 327 ring->funcs->emit_wave_limit(ring, false); 328 329 amdgpu_ring_ib_end(ring); 330 331 af->ib_dw_size = amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); 332 333 amdgpu_ring_commit(ring); 334 335 return 0; 336 337 free_fence: 338 if (!job) 339 kfree(af); 340 return r; 341 } 342 343 /** 344 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 345 * 346 * @adev: amdgpu_device pointer 347 * 348 * Initialize the suballocator to manage a pool of memory 349 * for use as IBs (all asics). 350 * Returns 0 on success, error on failure. 351 */ 352 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 353 { 354 const int sizes[AMDGPU_IB_POOL_MAX] = { 355 [AMDGPU_IB_POOL_DELAYED] = SZ_1M, 356 [AMDGPU_IB_POOL_IMMEDIATE] = SZ_128K, 357 [AMDGPU_IB_POOL_DIRECT] = SZ_512K 358 }; 359 const gfp_t gfp_flags[AMDGPU_IB_POOL_MAX] = { 360 /* 361 * For normal page table updates and recoverable retry faults 362 * (for SVM), further restricted by the VM eviction lock to not 363 * wait for memory reclaim. 364 */ 365 [AMDGPU_IB_POOL_DELAYED] = GFP_KERNEL, 366 /* 367 * For redirecting unrecoverable retry faults to the dummy page 368 * or set the PRT bits. dma_fence submissions might depend on 369 * that so we need the emmergency reserves. 370 */ 371 [AMDGPU_IB_POOL_IMMEDIATE] = GFP_ATOMIC, 372 /* 373 * For IB tests during GPU resets. Only very small and temporary 374 * allocation to allow dma_fences to signal. 375 */ 376 [AMDGPU_IB_POOL_DIRECT] = GFP_ATOMIC 377 }; 378 int r, i; 379 380 if (adev->ib_pool_ready) 381 return 0; 382 383 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 384 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 385 sizes[i], gfp_flags[i]); 386 if (r) 387 goto error; 388 } 389 adev->ib_pool_ready = true; 390 391 return 0; 392 393 error: 394 while (i--) 395 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 396 return r; 397 } 398 399 /** 400 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 401 * 402 * @adev: amdgpu_device pointer 403 * 404 * Tear down the suballocator managing the pool of memory 405 * for use as IBs (all asics). 406 */ 407 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 408 { 409 int i; 410 411 if (!adev->ib_pool_ready) 412 return; 413 414 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 415 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 416 adev->ib_pool_ready = false; 417 } 418 419 /** 420 * amdgpu_ib_pool_gfp_flags - Returns the gfp flags to use for each pool 421 * @adev: amdgpu device pointer 422 * @type: the IB pool type 423 */ 424 gfp_t amdgpu_ib_pool_gfp_flags(struct amdgpu_device *adev, 425 enum amdgpu_ib_pool_type type) 426 { 427 return adev->ib_pools[type].gfp_flags; 428 } 429 430 /** 431 * amdgpu_ib_ring_tests - test IBs on the rings 432 * 433 * @adev: amdgpu_device pointer 434 * 435 * Test an IB (Indirect Buffer) on each ring. 436 * If the test fails, disable the ring. 437 * Returns 0 on success, error if the primary GFX ring 438 * IB test fails. 439 */ 440 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 441 { 442 long tmo_gfx, tmo_mm; 443 int r, ret = 0; 444 unsigned int i; 445 446 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 447 if (amdgpu_sriov_vf(adev)) { 448 /* for MM engines in hypervisor side they are not scheduled together 449 * with CP and SDMA engines, so even in exclusive mode MM engine could 450 * still running on other VF thus the IB TEST TIMEOUT for MM engines 451 * under SR-IOV should be set to a long time. 8 sec should be enough 452 * for the MM comes back to this VF. 453 */ 454 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 455 } 456 457 if (amdgpu_sriov_runtime(adev)) { 458 /* for CP & SDMA engines since they are scheduled together so 459 * need to make the timeout width enough to cover the time 460 * cost waiting for it coming back under RUNTIME only 461 */ 462 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 463 } else if (adev->gmc.xgmi.hive_id) { 464 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 465 } 466 467 for (i = 0; i < adev->num_rings; ++i) { 468 struct amdgpu_ring *ring = adev->rings[i]; 469 long tmo; 470 471 /* KIQ rings don't have an IB test because we never submit IBs 472 * to them and they have no interrupt support. 473 */ 474 if (!ring->sched.ready || !ring->funcs->test_ib) 475 continue; 476 477 if (adev->enable_mes && 478 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 479 continue; 480 481 /* MM engine need more time */ 482 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 483 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 484 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 485 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 486 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 487 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 488 tmo = tmo_mm; 489 else 490 tmo = tmo_gfx; 491 492 r = amdgpu_ring_test_ib(ring, tmo); 493 if (!r) { 494 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 495 ring->name); 496 continue; 497 } 498 499 ring->sched.ready = false; 500 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 501 ring->name, r); 502 503 if (ring == &adev->gfx.gfx_ring[0]) { 504 /* oh, oh, that's really bad */ 505 adev->accel_working = false; 506 return r; 507 508 } else { 509 ret = r; 510 } 511 } 512 return ret; 513 } 514 515 /* 516 * Debugfs info 517 */ 518 #if defined(CONFIG_DEBUG_FS) 519 520 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused) 521 { 522 struct amdgpu_device *adev = m->private; 523 524 seq_puts(m, "--------------------- DELAYED ---------------------\n"); 525 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 526 m); 527 seq_puts(m, "-------------------- IMMEDIATE --------------------\n"); 528 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 529 m); 530 seq_puts(m, "--------------------- DIRECT ----------------------\n"); 531 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 532 533 return 0; 534 } 535 536 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info); 537 538 #endif 539 540 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 541 { 542 #if defined(CONFIG_DEBUG_FS) 543 struct drm_minor *minor = adev_to_drm(adev)->primary; 544 struct dentry *root = minor->debugfs_root; 545 546 debugfs_create_file("amdgpu_sa_info", 0444, root, adev, 547 &amdgpu_debugfs_sa_info_fops); 548 549 #endif 550 } 551