1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 48 #include <drm/ttm/ttm_bo.h> 49 #include <drm/ttm/ttm_placement.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_gem.h> 53 #include <drm/drm_ioctl.h> 54 55 #include <kgd_kfd_interface.h> 56 #include "dm_pp_interface.h" 57 #include "kgd_pp_interface.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_utils.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_vpe.h" 78 #include "amdgpu_umsch_mm.h" 79 #include "amdgpu_gmc.h" 80 #include "amdgpu_gfx.h" 81 #include "amdgpu_sdma.h" 82 #include "amdgpu_lsdma.h" 83 #include "amdgpu_nbio.h" 84 #include "amdgpu_hdp.h" 85 #include "amdgpu_dm.h" 86 #include "amdgpu_virt.h" 87 #include "amdgpu_csa.h" 88 #include "amdgpu_mes_ctx.h" 89 #include "amdgpu_gart.h" 90 #include "amdgpu_debugfs.h" 91 #include "amdgpu_job.h" 92 #include "amdgpu_bo_list.h" 93 #include "amdgpu_gem.h" 94 #include "amdgpu_doorbell.h" 95 #include "amdgpu_amdkfd.h" 96 #include "amdgpu_discovery.h" 97 #include "amdgpu_mes.h" 98 #include "amdgpu_umc.h" 99 #include "amdgpu_mmhub.h" 100 #include "amdgpu_gfxhub.h" 101 #include "amdgpu_df.h" 102 #include "amdgpu_smuio.h" 103 #include "amdgpu_fdinfo.h" 104 #include "amdgpu_mca.h" 105 #include "amdgpu_aca.h" 106 #include "amdgpu_ras.h" 107 #include "amdgpu_cper.h" 108 #include "amdgpu_xcp.h" 109 #include "amdgpu_seq64.h" 110 #include "amdgpu_reg_state.h" 111 #include "amdgpu_userq.h" 112 #include "amdgpu_eviction_fence.h" 113 #include "amdgpu_ip.h" 114 #if defined(CONFIG_DRM_AMD_ISP) 115 #include "amdgpu_isp.h" 116 #endif 117 118 #define MAX_GPU_INSTANCE 64 119 120 #define GFX_SLICE_PERIOD_MS 250 121 122 struct amdgpu_gpu_instance { 123 struct amdgpu_device *adev; 124 int mgpu_fan_enabled; 125 }; 126 127 struct amdgpu_mgpu_info { 128 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 129 struct mutex mutex; 130 uint32_t num_gpu; 131 uint32_t num_dgpu; 132 uint32_t num_apu; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_hwip_reg_entry { 143 u32 hwip; 144 u32 inst; 145 u32 seg; 146 u32 reg_offset; 147 const char *reg_name; 148 }; 149 150 struct amdgpu_watchdog_timer { 151 bool timeout_fatal_disable; 152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 153 }; 154 155 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 156 157 /* 158 * Modules parameters. 159 */ 160 extern int amdgpu_modeset; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern uint amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes_log_enable; 221 extern int amdgpu_uni_mes; 222 extern int amdgpu_noretry; 223 extern int amdgpu_force_asic_type; 224 extern int amdgpu_smartshift_bias; 225 extern int amdgpu_use_xgmi_p2p; 226 extern int amdgpu_mtype_local; 227 extern int amdgpu_enforce_isolation; 228 #ifdef CONFIG_HSA_AMD 229 extern int sched_policy; 230 extern bool debug_evictions; 231 extern bool no_system_mem_limit; 232 extern int halt_if_hws_hang; 233 extern uint amdgpu_svm_default_granularity; 234 #else 235 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 236 static const bool __maybe_unused debug_evictions; /* = false */ 237 static const bool __maybe_unused no_system_mem_limit; 238 static const int __maybe_unused halt_if_hws_hang; 239 #endif 240 #ifdef CONFIG_HSA_AMD_P2P 241 extern bool pcie_p2p; 242 #endif 243 244 extern int amdgpu_tmz; 245 extern int amdgpu_reset_method; 246 247 #ifdef CONFIG_DRM_AMDGPU_SI 248 extern int amdgpu_si_support; 249 #endif 250 #ifdef CONFIG_DRM_AMDGPU_CIK 251 extern int amdgpu_cik_support; 252 #endif 253 extern int amdgpu_num_kcq; 254 255 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 256 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 257 extern int amdgpu_vcnfw_log; 258 extern int amdgpu_sg_display; 259 extern int amdgpu_umsch_mm; 260 extern int amdgpu_seamless; 261 extern int amdgpu_umsch_mm_fwlog; 262 263 extern int amdgpu_user_partt_mode; 264 extern int amdgpu_agp; 265 extern int amdgpu_rebar; 266 267 extern int amdgpu_wbrf; 268 extern int amdgpu_user_queue; 269 270 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 271 272 #define AMDGPU_VM_MAX_NUM_CTX 4096 273 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 274 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 275 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 276 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 277 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 278 #define AMDGPUFB_CONN_LIMIT 4 279 #define AMDGPU_BIOS_NUM_SCRATCH 16 280 281 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 282 283 /* hard reset data */ 284 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 285 286 /* reset flags */ 287 #define AMDGPU_RESET_GFX (1 << 0) 288 #define AMDGPU_RESET_COMPUTE (1 << 1) 289 #define AMDGPU_RESET_DMA (1 << 2) 290 #define AMDGPU_RESET_CP (1 << 3) 291 #define AMDGPU_RESET_GRBM (1 << 4) 292 #define AMDGPU_RESET_DMA1 (1 << 5) 293 #define AMDGPU_RESET_RLC (1 << 6) 294 #define AMDGPU_RESET_SEM (1 << 7) 295 #define AMDGPU_RESET_IH (1 << 8) 296 #define AMDGPU_RESET_VMC (1 << 9) 297 #define AMDGPU_RESET_MC (1 << 10) 298 #define AMDGPU_RESET_DISPLAY (1 << 11) 299 #define AMDGPU_RESET_UVD (1 << 12) 300 #define AMDGPU_RESET_VCE (1 << 13) 301 #define AMDGPU_RESET_VCE1 (1 << 14) 302 303 /* reset mask */ 304 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 305 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 306 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 307 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 308 309 /* max cursor sizes (in pixels) */ 310 #define CIK_CURSOR_WIDTH 128 311 #define CIK_CURSOR_HEIGHT 128 312 313 /* smart shift bias level limits */ 314 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 315 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 316 317 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 318 #define AMDGPU_SWCTF_EXTRA_DELAY 50 319 320 struct amdgpu_xcp_mgr; 321 struct amdgpu_device; 322 struct amdgpu_irq_src; 323 struct amdgpu_fpriv; 324 struct amdgpu_bo_va_mapping; 325 struct kfd_vm_fault_info; 326 struct amdgpu_hive_info; 327 struct amdgpu_reset_context; 328 struct amdgpu_reset_control; 329 330 enum amdgpu_cp_irq { 331 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 332 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 333 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 334 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 341 342 AMDGPU_CP_IRQ_LAST 343 }; 344 345 enum amdgpu_thermal_irq { 346 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 347 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 348 349 AMDGPU_THERMAL_IRQ_LAST 350 }; 351 352 enum amdgpu_kiq_irq { 353 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 354 AMDGPU_CP_KIQ_IRQ_LAST 355 }; 356 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 357 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 358 #define MAX_KIQ_REG_TRY 1000 359 360 /* 361 * BIOS. 362 */ 363 bool amdgpu_get_bios(struct amdgpu_device *adev); 364 bool amdgpu_read_bios(struct amdgpu_device *adev); 365 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 366 u8 *bios, u32 length_bytes); 367 void amdgpu_bios_release(struct amdgpu_device *adev); 368 /* 369 * Clocks 370 */ 371 372 #define AMDGPU_MAX_PPLL 3 373 374 struct amdgpu_clock { 375 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 376 struct amdgpu_pll spll; 377 struct amdgpu_pll mpll; 378 /* 10 Khz units */ 379 uint32_t default_mclk; 380 uint32_t default_sclk; 381 uint32_t default_dispclk; 382 uint32_t dp_extclk; 383 uint32_t max_pixel_clock; 384 }; 385 386 /* sub-allocation manager, it has to be protected by another lock. 387 * By conception this is an helper for other part of the driver 388 * like the indirect buffer or semaphore, which both have their 389 * locking. 390 * 391 * Principe is simple, we keep a list of sub allocation in offset 392 * order (first entry has offset == 0, last entry has the highest 393 * offset). 394 * 395 * When allocating new object we first check if there is room at 396 * the end total_size - (last_object_offset + last_object_size) >= 397 * alloc_size. If so we allocate new object there. 398 * 399 * When there is not enough room at the end, we start waiting for 400 * each sub object until we reach object_offset+object_size >= 401 * alloc_size, this object then become the sub object we return. 402 * 403 * Alignment can't be bigger than page size. 404 * 405 * Hole are not considered for allocation to keep things simple. 406 * Assumption is that there won't be hole (all object on same 407 * alignment). 408 */ 409 410 struct amdgpu_sa_manager { 411 struct drm_suballoc_manager base; 412 struct amdgpu_bo *bo; 413 uint64_t gpu_addr; 414 void *cpu_ptr; 415 }; 416 417 /* 418 * IRQS. 419 */ 420 421 struct amdgpu_flip_work { 422 struct delayed_work flip_work; 423 struct work_struct unpin_work; 424 struct amdgpu_device *adev; 425 int crtc_id; 426 u32 target_vblank; 427 uint64_t base; 428 struct drm_pending_vblank_event *event; 429 struct amdgpu_bo *old_abo; 430 unsigned shared_count; 431 struct dma_fence **shared; 432 struct dma_fence_cb cb; 433 bool async; 434 }; 435 436 /* 437 * file private structure 438 */ 439 440 struct amdgpu_fpriv { 441 struct amdgpu_vm vm; 442 struct amdgpu_bo_va *prt_va; 443 struct amdgpu_bo_va *csa_va; 444 struct amdgpu_bo_va *seq64_va; 445 struct mutex bo_list_lock; 446 struct idr bo_list_handles; 447 struct amdgpu_ctx_mgr ctx_mgr; 448 struct amdgpu_userq_mgr userq_mgr; 449 450 /* Eviction fence infra */ 451 struct amdgpu_eviction_fence_mgr evf_mgr; 452 453 /** GPU partition selection */ 454 uint32_t xcp_id; 455 }; 456 457 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 458 459 /* 460 * Writeback 461 */ 462 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 463 464 /** 465 * amdgpu_wb - This struct is used for small GPU memory allocation. 466 * 467 * This struct is used to allocate a small amount of GPU memory that can be 468 * used to shadow certain states into the memory. This is especially useful for 469 * providing easy CPU access to some states without requiring register access 470 * (e.g., if some block is power gated, reading register may be problematic). 471 * 472 * Note: the term writeback was initially used because many of the amdgpu 473 * components had some level of writeback memory, and this struct initially 474 * described those components. 475 */ 476 struct amdgpu_wb { 477 478 /** 479 * @wb_obj: 480 * 481 * Buffer Object used for the writeback memory. 482 */ 483 struct amdgpu_bo *wb_obj; 484 485 /** 486 * @wb: 487 * 488 * Pointer to the first writeback slot. In terms of CPU address 489 * this value can be accessed directly by using the offset as an index. 490 * For the GPU address, it is necessary to use gpu_addr and the offset. 491 */ 492 uint32_t *wb; 493 494 /** 495 * @gpu_addr: 496 * 497 * Writeback base address in the GPU. 498 */ 499 uint64_t gpu_addr; 500 501 /** 502 * @num_wb: 503 * 504 * Number of writeback slots reserved for amdgpu. 505 */ 506 u32 num_wb; 507 508 /** 509 * @used: 510 * 511 * Track the writeback slot already used. 512 */ 513 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 514 515 /** 516 * @lock: 517 * 518 * Protects read and write of the used field array. 519 */ 520 spinlock_t lock; 521 }; 522 523 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 524 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 525 526 /* 527 * Benchmarking 528 */ 529 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 530 531 /* 532 * ASIC specific register table accessible by UMD 533 */ 534 struct amdgpu_allowed_register_entry { 535 uint32_t reg_offset; 536 bool grbm_indexed; 537 }; 538 539 /** 540 * enum amd_reset_method - Methods for resetting AMD GPU devices 541 * 542 * @AMD_RESET_METHOD_NONE: The device will not be reset. 543 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 544 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 545 * any device. 546 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 547 * individually. Suitable only for some discrete GPU, not 548 * available for all ASICs. 549 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 550 * are reset depends on the ASIC. Notably doesn't reset IPs 551 * shared with the CPU on APUs or the memory controllers (so 552 * VRAM is not lost). Not available on all ASICs. 553 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 554 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 555 * but without powering off the PCI bus. Suitable only for 556 * discrete GPUs. 557 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 558 * and does a secondary bus reset or FLR, depending on what the 559 * underlying hardware supports. 560 * 561 * Methods available for AMD GPU driver for resetting the device. Not all 562 * methods are suitable for every device. User can override the method using 563 * module parameter `reset_method`. 564 */ 565 enum amd_reset_method { 566 AMD_RESET_METHOD_NONE = -1, 567 AMD_RESET_METHOD_LEGACY = 0, 568 AMD_RESET_METHOD_MODE0, 569 AMD_RESET_METHOD_MODE1, 570 AMD_RESET_METHOD_MODE2, 571 AMD_RESET_METHOD_LINK, 572 AMD_RESET_METHOD_BACO, 573 AMD_RESET_METHOD_PCI, 574 AMD_RESET_METHOD_ON_INIT, 575 }; 576 577 struct amdgpu_video_codec_info { 578 u32 codec_type; 579 u32 max_width; 580 u32 max_height; 581 u32 max_pixels_per_frame; 582 u32 max_level; 583 }; 584 585 #define codec_info_build(type, width, height, level) \ 586 .codec_type = type,\ 587 .max_width = width,\ 588 .max_height = height,\ 589 .max_pixels_per_frame = height * width,\ 590 .max_level = level, 591 592 struct amdgpu_video_codecs { 593 const u32 codec_count; 594 const struct amdgpu_video_codec_info *codec_array; 595 }; 596 597 /* 598 * ASIC specific functions. 599 */ 600 struct amdgpu_asic_funcs { 601 bool (*read_disabled_bios)(struct amdgpu_device *adev); 602 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 603 u8 *bios, u32 length_bytes); 604 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 605 u32 sh_num, u32 reg_offset, u32 *value); 606 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 607 int (*reset)(struct amdgpu_device *adev); 608 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 609 /* get the reference clock */ 610 u32 (*get_xclk)(struct amdgpu_device *adev); 611 /* MM block clocks */ 612 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 613 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 614 /* static power management */ 615 int (*get_pcie_lanes)(struct amdgpu_device *adev); 616 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 617 /* get config memsize register */ 618 u32 (*get_config_memsize)(struct amdgpu_device *adev); 619 /* flush hdp write queue */ 620 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 621 /* invalidate hdp read cache */ 622 void (*invalidate_hdp)(struct amdgpu_device *adev, 623 struct amdgpu_ring *ring); 624 /* check if the asic needs a full reset of if soft reset will work */ 625 bool (*need_full_reset)(struct amdgpu_device *adev); 626 /* initialize doorbell layout for specific asic*/ 627 void (*init_doorbell_index)(struct amdgpu_device *adev); 628 /* PCIe bandwidth usage */ 629 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 630 uint64_t *count1); 631 /* do we need to reset the asic at init time (e.g., kexec) */ 632 bool (*need_reset_on_init)(struct amdgpu_device *adev); 633 /* PCIe replay counter */ 634 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 635 /* device supports BACO */ 636 int (*supports_baco)(struct amdgpu_device *adev); 637 /* pre asic_init quirks */ 638 void (*pre_asic_init)(struct amdgpu_device *adev); 639 /* enter/exit umd stable pstate */ 640 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 641 /* query video codecs */ 642 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 643 const struct amdgpu_video_codecs **codecs); 644 /* encode "> 32bits" smn addressing */ 645 u64 (*encode_ext_smn_addressing)(int ext_id); 646 647 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 648 enum amdgpu_reg_state reg_state, void *buf, 649 size_t max_size); 650 }; 651 652 /* 653 * IOCTL. 654 */ 655 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 656 struct drm_file *filp); 657 658 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 659 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 660 struct drm_file *filp); 661 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 662 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 663 struct drm_file *filp); 664 665 /* VRAM scratch page for HDP bug, default vram page */ 666 struct amdgpu_mem_scratch { 667 struct amdgpu_bo *robj; 668 uint32_t *ptr; 669 u64 gpu_addr; 670 }; 671 672 /* 673 * CGS 674 */ 675 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 676 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 677 678 /* 679 * Core structure, functions and helpers. 680 */ 681 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 682 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 683 684 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 685 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 686 687 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 688 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 689 690 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 691 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 692 693 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 694 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 695 696 struct amdgpu_mmio_remap { 697 u32 reg_offset; 698 resource_size_t bus_addr; 699 struct amdgpu_bo *bo; 700 }; 701 702 enum amdgpu_uid_type { 703 AMDGPU_UID_TYPE_XCD, 704 AMDGPU_UID_TYPE_AID, 705 AMDGPU_UID_TYPE_SOC, 706 AMDGPU_UID_TYPE_MAX 707 }; 708 709 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 710 711 struct amdgpu_uid { 712 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 713 struct amdgpu_device *adev; 714 }; 715 716 #define MAX_UMA_OPTION_NAME 28 717 #define MAX_UMA_OPTION_ENTRIES 19 718 719 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 720 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 721 722 /** 723 * struct amdgpu_uma_carveout_option - single UMA carveout option 724 * @name: Name of the carveout option 725 * @memory_carved_mb: Amount of memory carved in MB 726 * @flags: ATCS flags supported by this option 727 */ 728 struct amdgpu_uma_carveout_option { 729 char name[MAX_UMA_OPTION_NAME]; 730 uint32_t memory_carved_mb; 731 uint8_t flags; 732 }; 733 734 /** 735 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 736 * @num_entries: Number of available options 737 * @uma_option_index: The index of the option currently applied 738 * @update_lock: Lock to serialize changes to the option 739 * @entries: The array of carveout options 740 */ 741 struct amdgpu_uma_carveout_info { 742 uint8_t num_entries; 743 uint8_t uma_option_index; 744 struct mutex update_lock; 745 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 746 }; 747 748 struct amd_powerplay { 749 void *pp_handle; 750 const struct amd_pm_funcs *pp_funcs; 751 }; 752 753 /* polaris10 kickers */ 754 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 755 ((rid == 0xE3) || \ 756 (rid == 0xE4) || \ 757 (rid == 0xE5) || \ 758 (rid == 0xE7) || \ 759 (rid == 0xEF))) || \ 760 ((did == 0x6FDF) && \ 761 ((rid == 0xE7) || \ 762 (rid == 0xEF) || \ 763 (rid == 0xFF)))) 764 765 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 766 ((rid == 0xE1) || \ 767 (rid == 0xF7))) 768 769 /* polaris11 kickers */ 770 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 771 ((rid == 0xE0) || \ 772 (rid == 0xE5))) || \ 773 ((did == 0x67FF) && \ 774 ((rid == 0xCF) || \ 775 (rid == 0xEF) || \ 776 (rid == 0xFF)))) 777 778 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 779 ((rid == 0xE2))) 780 781 /* polaris12 kickers */ 782 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 783 ((rid == 0xC0) || \ 784 (rid == 0xC1) || \ 785 (rid == 0xC3) || \ 786 (rid == 0xC7))) || \ 787 ((did == 0x6981) && \ 788 ((rid == 0x00) || \ 789 (rid == 0x01) || \ 790 (rid == 0x10)))) 791 792 enum amdgpu_mqd_update_flag { 793 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 794 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 795 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 796 }; 797 798 struct amdgpu_mqd_prop { 799 uint64_t mqd_gpu_addr; 800 uint64_t hqd_base_gpu_addr; 801 uint64_t rptr_gpu_addr; 802 uint64_t wptr_gpu_addr; 803 uint32_t queue_size; 804 bool use_doorbell; 805 uint32_t doorbell_index; 806 uint64_t eop_gpu_addr; 807 uint32_t hqd_pipe_priority; 808 uint32_t hqd_queue_priority; 809 uint32_t mqd_stride_size; 810 bool allow_tunneling; 811 bool hqd_active; 812 uint64_t shadow_addr; 813 uint64_t gds_bkup_addr; 814 uint64_t csa_addr; 815 uint64_t fence_address; 816 bool tmz_queue; 817 bool kernel_queue; 818 uint32_t *cu_mask; 819 uint32_t cu_mask_count; 820 uint32_t cu_flags; 821 bool is_user_cu_masked; 822 }; 823 824 struct amdgpu_mqd { 825 unsigned mqd_size; 826 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 827 struct amdgpu_mqd_prop *p); 828 }; 829 830 struct amdgpu_pcie_reset_ctx { 831 bool in_link_reset; 832 bool occurs_dpc; 833 bool audio_suspended; 834 struct pci_dev *swus; 835 struct pci_saved_state *swus_pcistate; 836 struct pci_saved_state *swds_pcistate; 837 }; 838 839 /* 840 * Custom Init levels could be defined for different situations where a full 841 * initialization of all hardware blocks are not expected. Sample cases are 842 * custom init sequences after resume after S0i3/S3, reset on initialization, 843 * partial reset of blocks etc. Presently, this defines only two levels. Levels 844 * are described in corresponding struct definitions - amdgpu_init_default, 845 * amdgpu_init_minimal_xgmi. 846 */ 847 enum amdgpu_init_lvl_id { 848 AMDGPU_INIT_LEVEL_DEFAULT, 849 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 850 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 851 }; 852 853 struct amdgpu_init_level { 854 enum amdgpu_init_lvl_id level; 855 uint32_t hwini_ip_block_mask; 856 }; 857 858 #define AMDGPU_RESET_MAGIC_NUM 64 859 #define AMDGPU_MAX_DF_PERFMONS 4 860 struct amdgpu_reset_domain; 861 struct amdgpu_fru_info; 862 863 enum amdgpu_enforce_isolation_mode { 864 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 865 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 866 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 867 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 868 }; 869 870 struct amdgpu_device { 871 struct device *dev; 872 struct pci_dev *pdev; 873 struct drm_device ddev; 874 875 #ifdef CONFIG_DRM_AMD_ACP 876 struct amdgpu_acp acp; 877 #endif 878 struct amdgpu_hive_info *hive; 879 struct amdgpu_xcp_mgr *xcp_mgr; 880 /* ASIC */ 881 enum amd_asic_type asic_type; 882 uint32_t family; 883 uint32_t rev_id; 884 uint32_t external_rev_id; 885 unsigned long flags; 886 unsigned long apu_flags; 887 int usec_timeout; 888 const struct amdgpu_asic_funcs *asic_funcs; 889 bool shutdown; 890 bool need_swiotlb; 891 bool accel_working; 892 struct notifier_block acpi_nb; 893 struct notifier_block pm_nb; 894 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 895 struct debugfs_blob_wrapper debugfs_vbios_blob; 896 struct mutex srbm_mutex; 897 /* GRBM index mutex. Protects concurrent access to GRBM index */ 898 struct mutex grbm_idx_mutex; 899 struct dev_pm_domain vga_pm_domain; 900 bool have_disp_power_ref; 901 bool have_atomics_support; 902 903 /* BIOS */ 904 bool is_atom_fw; 905 uint8_t *bios; 906 uint32_t bios_size; 907 uint32_t bios_scratch_reg_offset; 908 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 909 910 /* Register/doorbell mmio */ 911 resource_size_t rmmio_base; 912 resource_size_t rmmio_size; 913 void __iomem *rmmio; 914 /* protects concurrent MM_INDEX/DATA based register access */ 915 spinlock_t mmio_idx_lock; 916 struct amdgpu_mmio_remap rmmio_remap; 917 /* protects concurrent SMC based register access */ 918 spinlock_t smc_idx_lock; 919 amdgpu_rreg_t smc_rreg; 920 amdgpu_wreg_t smc_wreg; 921 /* protects concurrent PCIE register access */ 922 spinlock_t pcie_idx_lock; 923 amdgpu_rreg_t pcie_rreg; 924 amdgpu_wreg_t pcie_wreg; 925 amdgpu_rreg_t pciep_rreg; 926 amdgpu_wreg_t pciep_wreg; 927 amdgpu_rreg_ext_t pcie_rreg_ext; 928 amdgpu_wreg_ext_t pcie_wreg_ext; 929 amdgpu_rreg64_t pcie_rreg64; 930 amdgpu_wreg64_t pcie_wreg64; 931 amdgpu_rreg64_ext_t pcie_rreg64_ext; 932 amdgpu_wreg64_ext_t pcie_wreg64_ext; 933 /* protects concurrent UVD register access */ 934 spinlock_t uvd_ctx_idx_lock; 935 amdgpu_rreg_t uvd_ctx_rreg; 936 amdgpu_wreg_t uvd_ctx_wreg; 937 /* protects concurrent DIDT register access */ 938 spinlock_t didt_idx_lock; 939 amdgpu_rreg_t didt_rreg; 940 amdgpu_wreg_t didt_wreg; 941 /* protects concurrent gc_cac register access */ 942 spinlock_t gc_cac_idx_lock; 943 amdgpu_rreg_t gc_cac_rreg; 944 amdgpu_wreg_t gc_cac_wreg; 945 /* protects concurrent se_cac register access */ 946 spinlock_t se_cac_idx_lock; 947 amdgpu_rreg_t se_cac_rreg; 948 amdgpu_wreg_t se_cac_wreg; 949 /* protects concurrent ENDPOINT (audio) register access */ 950 spinlock_t audio_endpt_idx_lock; 951 amdgpu_block_rreg_t audio_endpt_rreg; 952 amdgpu_block_wreg_t audio_endpt_wreg; 953 struct amdgpu_doorbell doorbell; 954 955 /* clock/pll info */ 956 struct amdgpu_clock clock; 957 958 /* MC */ 959 struct amdgpu_gmc gmc; 960 struct amdgpu_gart gart; 961 dma_addr_t dummy_page_addr; 962 struct amdgpu_vm_manager vm_manager; 963 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 964 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 965 966 /* memory management */ 967 struct amdgpu_mman mman; 968 struct amdgpu_mem_scratch mem_scratch; 969 struct amdgpu_wb wb; 970 atomic64_t num_bytes_moved; 971 atomic64_t num_evictions; 972 atomic64_t num_vram_cpu_page_faults; 973 atomic_t gpu_reset_counter; 974 atomic_t vram_lost_counter; 975 976 /* data for buffer migration throttling */ 977 struct { 978 spinlock_t lock; 979 s64 last_update_us; 980 s64 accum_us; /* accumulated microseconds */ 981 s64 accum_us_vis; /* for visible VRAM */ 982 u32 log2_max_MBps; 983 } mm_stats; 984 985 /* discovery*/ 986 struct amdgpu_discovery_info discovery; 987 988 /* display */ 989 bool enable_virtual_display; 990 struct amdgpu_vkms_output *amdgpu_vkms_output; 991 struct amdgpu_mode_info mode_info; 992 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 993 struct delayed_work hotplug_work; 994 struct amdgpu_irq_src crtc_irq; 995 struct amdgpu_irq_src vline0_irq; 996 struct amdgpu_irq_src vupdate_irq; 997 struct amdgpu_irq_src pageflip_irq; 998 struct amdgpu_irq_src hpd_irq; 999 struct amdgpu_irq_src dmub_trace_irq; 1000 struct amdgpu_irq_src dmub_outbox_irq; 1001 1002 /* rings */ 1003 u64 fence_context; 1004 unsigned num_rings; 1005 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1006 struct dma_fence __rcu *gang_submit; 1007 bool ib_pool_ready; 1008 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1009 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1010 1011 /* interrupts */ 1012 struct amdgpu_irq irq; 1013 1014 /* powerplay */ 1015 struct amd_powerplay powerplay; 1016 struct amdgpu_pm pm; 1017 u64 cg_flags; 1018 u32 pg_flags; 1019 1020 /* nbio */ 1021 struct amdgpu_nbio nbio; 1022 1023 /* hdp */ 1024 struct amdgpu_hdp hdp; 1025 1026 /* smuio */ 1027 struct amdgpu_smuio smuio; 1028 1029 /* mmhub */ 1030 struct amdgpu_mmhub mmhub; 1031 1032 /* gfxhub */ 1033 struct amdgpu_gfxhub gfxhub; 1034 1035 /* gfx */ 1036 struct amdgpu_gfx gfx; 1037 1038 /* sdma */ 1039 struct amdgpu_sdma sdma; 1040 1041 /* lsdma */ 1042 struct amdgpu_lsdma lsdma; 1043 1044 /* uvd */ 1045 struct amdgpu_uvd uvd; 1046 1047 /* vce */ 1048 struct amdgpu_vce vce; 1049 1050 /* vcn */ 1051 struct amdgpu_vcn vcn; 1052 1053 /* jpeg */ 1054 struct amdgpu_jpeg jpeg; 1055 1056 /* vpe */ 1057 struct amdgpu_vpe vpe; 1058 1059 /* umsch */ 1060 struct amdgpu_umsch_mm umsch_mm; 1061 bool enable_umsch_mm; 1062 1063 /* firmwares */ 1064 struct amdgpu_firmware firmware; 1065 1066 /* PSP */ 1067 struct psp_context psp; 1068 1069 /* GDS */ 1070 struct amdgpu_gds gds; 1071 1072 /* for userq and VM fences */ 1073 struct amdgpu_seq64 seq64; 1074 1075 /* UMC */ 1076 struct amdgpu_umc umc; 1077 1078 /* display related functionality */ 1079 struct amdgpu_display_manager dm; 1080 1081 #if defined(CONFIG_DRM_AMD_ISP) 1082 /* isp */ 1083 struct amdgpu_isp isp; 1084 #endif 1085 1086 /* mes */ 1087 bool enable_mes; 1088 bool enable_mes_kiq; 1089 bool enable_uni_mes; 1090 struct amdgpu_mes mes; 1091 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1092 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1093 1094 /* xarray used to retrieve the user queue fence driver reference 1095 * in the EOP interrupt handler to signal the particular user 1096 * queue fence. 1097 */ 1098 struct xarray userq_xa; 1099 /** 1100 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1101 * Key: doorbell_index (unique global identifier for the queue) 1102 * Value: struct amdgpu_usermode_queue 1103 */ 1104 struct xarray userq_doorbell_xa; 1105 1106 /* df */ 1107 struct amdgpu_df df; 1108 1109 /* MCA */ 1110 struct amdgpu_mca mca; 1111 1112 /* ACA */ 1113 struct amdgpu_aca aca; 1114 1115 /* CPER */ 1116 struct amdgpu_cper cper; 1117 1118 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1119 uint32_t harvest_ip_mask; 1120 int num_ip_blocks; 1121 struct mutex mn_lock; 1122 DECLARE_HASHTABLE(mn_hash, 7); 1123 1124 /* tracking pinned memory */ 1125 atomic64_t vram_pin_size; 1126 atomic64_t visible_pin_size; 1127 atomic64_t gart_pin_size; 1128 1129 /* soc15 register offset based on ip, instance and segment */ 1130 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1131 struct amdgpu_ip_map_info ip_map; 1132 1133 /* delayed work_func for deferring clockgating during resume */ 1134 struct delayed_work delayed_init_work; 1135 1136 struct amdgpu_virt virt; 1137 1138 /* record hw reset is performed */ 1139 bool has_hw_reset; 1140 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1141 1142 /* s3/s4 mask */ 1143 bool in_suspend; 1144 bool in_s3; 1145 bool in_s4; 1146 bool in_s0ix; 1147 suspend_state_t last_suspend_state; 1148 1149 enum pp_mp1_state mp1_state; 1150 struct amdgpu_doorbell_index doorbell_index; 1151 1152 struct mutex notifier_lock; 1153 1154 int asic_reset_res; 1155 struct work_struct xgmi_reset_work; 1156 struct list_head reset_list; 1157 1158 long gfx_timeout; 1159 long sdma_timeout; 1160 long video_timeout; 1161 long compute_timeout; 1162 long psp_timeout; 1163 1164 uint64_t unique_id; 1165 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1166 1167 /* enable runtime pm on the device */ 1168 bool in_runpm; 1169 bool has_pr3; 1170 1171 bool ucode_sysfs_en; 1172 1173 struct amdgpu_fru_info *fru_info; 1174 atomic_t throttling_logging_enabled; 1175 struct ratelimit_state throttling_logging_rs; 1176 uint32_t ras_hw_enabled; 1177 uint32_t ras_enabled; 1178 bool ras_default_ecc_enabled; 1179 1180 bool no_hw_access; 1181 struct pci_saved_state *pci_state; 1182 pci_channel_state_t pci_channel_state; 1183 1184 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1185 1186 /* Track auto wait count on s_barrier settings */ 1187 bool barrier_has_auto_waitcnt; 1188 1189 struct amdgpu_reset_control *reset_cntl; 1190 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1191 1192 bool ram_is_direct_mapped; 1193 1194 struct list_head ras_list; 1195 1196 struct amdgpu_reset_domain *reset_domain; 1197 1198 struct mutex benchmark_mutex; 1199 1200 bool scpm_enabled; 1201 uint32_t scpm_status; 1202 1203 struct work_struct reset_work; 1204 1205 bool dc_enabled; 1206 /* Mask of active clusters */ 1207 uint32_t aid_mask; 1208 1209 /* Debug */ 1210 bool debug_vm; 1211 bool debug_largebar; 1212 bool debug_disable_soft_recovery; 1213 bool debug_use_vram_fw_buf; 1214 bool debug_enable_ras_aca; 1215 bool debug_exp_resets; 1216 bool debug_disable_gpu_ring_reset; 1217 bool debug_vm_userptr; 1218 bool debug_disable_ce_logs; 1219 bool debug_enable_ce_cs; 1220 1221 /* Protection for the following isolation structure */ 1222 struct mutex enforce_isolation_mutex; 1223 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1224 struct amdgpu_isolation { 1225 void *owner; 1226 struct dma_fence *spearhead; 1227 struct amdgpu_sync active; 1228 struct amdgpu_sync prev; 1229 } isolation[MAX_XCP]; 1230 1231 struct amdgpu_init_level *init_lvl; 1232 1233 /* This flag is used to determine how VRAM allocations are handled for APUs 1234 * in KFD: VRAM or GTT. 1235 */ 1236 bool apu_prefer_gtt; 1237 1238 bool userq_halt_for_enforce_isolation; 1239 struct work_struct userq_reset_work; 1240 struct amdgpu_uid *uid_info; 1241 1242 struct amdgpu_uma_carveout_info uma_info; 1243 1244 /* KFD 1245 * Must be last --ends in a flexible-array member. 1246 */ 1247 struct amdgpu_kfd_dev kfd; 1248 }; 1249 1250 /* 1251 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1252 * as fence address and writes a 32 bit fence value to this address. 1253 * Driver needs to allocate at least 4 DWs extra memory in addition to 1254 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1255 */ 1256 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1257 1258 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1259 uint8_t ip, uint8_t inst) 1260 { 1261 /* This considers only major/minor/rev and ignores 1262 * subrevision/variant fields. 1263 */ 1264 return adev->ip_versions[ip][inst] & ~0xFFU; 1265 } 1266 1267 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1268 uint8_t ip, uint8_t inst) 1269 { 1270 /* This returns full version - major/minor/rev/variant/subrevision */ 1271 return adev->ip_versions[ip][inst]; 1272 } 1273 1274 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1275 { 1276 return container_of(ddev, struct amdgpu_device, ddev); 1277 } 1278 1279 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1280 { 1281 return &adev->ddev; 1282 } 1283 1284 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1285 { 1286 return container_of(bdev, struct amdgpu_device, mman.bdev); 1287 } 1288 1289 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1290 { 1291 return !!adev->aid_mask; 1292 } 1293 1294 int amdgpu_device_init(struct amdgpu_device *adev, 1295 uint32_t flags); 1296 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1297 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1298 1299 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1300 1301 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1302 void *buf, size_t size, bool write); 1303 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1304 void *buf, size_t size, bool write); 1305 1306 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1307 void *buf, size_t size, bool write); 1308 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1309 uint32_t inst, uint32_t reg_addr, char reg_name[], 1310 uint32_t expected_value, uint32_t mask); 1311 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1312 uint32_t reg, uint32_t acc_flags); 1313 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1314 u64 reg_addr); 1315 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1316 uint32_t reg, uint32_t acc_flags, 1317 uint32_t xcc_id); 1318 void amdgpu_device_wreg(struct amdgpu_device *adev, 1319 uint32_t reg, uint32_t v, 1320 uint32_t acc_flags); 1321 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1322 u64 reg_addr, u32 reg_data); 1323 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1324 uint32_t reg, uint32_t v, 1325 uint32_t acc_flags, 1326 uint32_t xcc_id); 1327 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1328 uint32_t reg, uint32_t v, uint32_t xcc_id); 1329 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1330 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1331 1332 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1333 u32 reg_addr); 1334 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1335 u32 reg_addr); 1336 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1337 u64 reg_addr); 1338 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1339 u32 reg_addr, u32 reg_data); 1340 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1341 u32 reg_addr, u64 reg_data); 1342 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1343 u64 reg_addr, u64 reg_data); 1344 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1345 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1346 enum amd_asic_type asic_type); 1347 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1348 1349 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1350 1351 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1352 struct amdgpu_reset_context *reset_context); 1353 1354 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1355 struct amdgpu_reset_context *reset_context); 1356 1357 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1358 1359 int emu_soc_asic_init(struct amdgpu_device *adev); 1360 1361 /* 1362 * Registers read & write functions. 1363 */ 1364 #define AMDGPU_REGS_NO_KIQ (1<<1) 1365 #define AMDGPU_REGS_RLC (1<<2) 1366 1367 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1368 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1369 1370 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1371 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1372 1373 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1374 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1375 1376 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1377 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1378 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1379 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1380 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1381 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1382 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1383 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1384 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1385 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1386 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1387 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1388 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1389 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1390 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1391 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1392 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1393 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1394 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1395 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1396 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1397 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1398 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1399 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1400 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1401 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1402 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1403 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1404 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1405 #define WREG32_P(reg, val, mask) \ 1406 do { \ 1407 uint32_t tmp_ = RREG32(reg); \ 1408 tmp_ &= (mask); \ 1409 tmp_ |= ((val) & ~(mask)); \ 1410 WREG32(reg, tmp_); \ 1411 } while (0) 1412 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1413 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1414 #define WREG32_PLL_P(reg, val, mask) \ 1415 do { \ 1416 uint32_t tmp_ = RREG32_PLL(reg); \ 1417 tmp_ &= (mask); \ 1418 tmp_ |= ((val) & ~(mask)); \ 1419 WREG32_PLL(reg, tmp_); \ 1420 } while (0) 1421 1422 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1423 do { \ 1424 u32 tmp = RREG32_SMC(_Reg); \ 1425 tmp &= (_Mask); \ 1426 tmp |= ((_Val) & ~(_Mask)); \ 1427 WREG32_SMC(_Reg, tmp); \ 1428 } while (0) 1429 1430 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1431 1432 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1433 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1434 1435 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1436 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1437 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1438 1439 #define REG_GET_FIELD(value, reg, field) \ 1440 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1441 1442 #define WREG32_FIELD(reg, field, val) \ 1443 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1444 1445 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1446 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1447 1448 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1449 /* 1450 * BIOS helpers. 1451 */ 1452 #define RBIOS8(i) (adev->bios[i]) 1453 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1454 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1455 1456 /* 1457 * ASICs macro. 1458 */ 1459 #define amdgpu_asic_set_vga_state(adev, state) \ 1460 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1461 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1462 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1463 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1464 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1465 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1466 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1467 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1468 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1469 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1470 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1471 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1472 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1473 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1474 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1475 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1476 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1477 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1478 #define amdgpu_asic_supports_baco(adev) \ 1479 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1480 #define amdgpu_asic_pre_asic_init(adev) \ 1481 { \ 1482 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1483 (adev)->asic_funcs->pre_asic_init((adev)); \ 1484 } 1485 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1486 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1487 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1488 1489 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1490 1491 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1492 #define for_each_inst(i, inst_mask) \ 1493 for (i = ffs(inst_mask); i-- != 0; \ 1494 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1495 1496 /* Common functions */ 1497 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1498 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1499 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1500 struct amdgpu_job *job, 1501 struct amdgpu_reset_context *reset_context); 1502 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1503 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1504 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1505 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1506 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1507 1508 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1509 u64 num_vis_bytes); 1510 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1511 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1512 const u32 *registers, 1513 const u32 array_size); 1514 1515 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1516 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1517 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1518 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1519 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1520 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1521 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1522 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1523 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1524 struct amdgpu_device *peer_adev); 1525 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1526 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1527 1528 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1529 struct amdgpu_ring *ring); 1530 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1531 struct amdgpu_ring *ring); 1532 1533 void amdgpu_device_halt(struct amdgpu_device *adev); 1534 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1535 u32 reg); 1536 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1537 u32 reg, u32 v); 1538 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1539 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1540 struct dma_fence *gang); 1541 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1542 struct amdgpu_ring *ring, 1543 struct amdgpu_job *job); 1544 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1545 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1546 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1547 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1548 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1549 1550 /* atpx handler */ 1551 #if defined(CONFIG_VGA_SWITCHEROO) 1552 void amdgpu_register_atpx_handler(void); 1553 void amdgpu_unregister_atpx_handler(void); 1554 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1555 bool amdgpu_is_atpx_hybrid(void); 1556 bool amdgpu_has_atpx(void); 1557 #else 1558 static inline void amdgpu_register_atpx_handler(void) {} 1559 static inline void amdgpu_unregister_atpx_handler(void) {} 1560 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1561 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1562 static inline bool amdgpu_has_atpx(void) { return false; } 1563 #endif 1564 1565 /* 1566 * KMS 1567 */ 1568 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1569 extern const int amdgpu_max_kms_ioctl; 1570 1571 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1572 void amdgpu_driver_unload_kms(struct drm_device *dev); 1573 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1574 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1575 struct drm_file *file_priv); 1576 void amdgpu_driver_release_kms(struct drm_device *dev); 1577 1578 int amdgpu_device_prepare(struct drm_device *dev); 1579 void amdgpu_device_complete(struct drm_device *dev); 1580 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1581 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1582 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1583 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1584 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1585 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1586 struct drm_file *filp); 1587 1588 /* 1589 * functions used by amdgpu_encoder.c 1590 */ 1591 struct amdgpu_afmt_acr { 1592 u32 clock; 1593 1594 int n_32khz; 1595 int cts_32khz; 1596 1597 int n_44_1khz; 1598 int cts_44_1khz; 1599 1600 int n_48khz; 1601 int cts_48khz; 1602 1603 }; 1604 1605 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1606 1607 /* amdgpu_acpi.c */ 1608 1609 struct amdgpu_numa_info { 1610 uint64_t size; 1611 int pxm; 1612 int nid; 1613 }; 1614 1615 /* ATCS Device/Driver State */ 1616 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1617 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1618 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1619 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1620 1621 #if defined(CONFIG_ACPI) 1622 int amdgpu_acpi_init(struct amdgpu_device *adev); 1623 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1624 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1625 bool amdgpu_acpi_is_power_shift_control_supported(void); 1626 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1627 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1628 u8 perf_req, bool advertise); 1629 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1630 u8 dev_state, bool drv_state); 1631 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1632 enum amdgpu_ss ss_state); 1633 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1634 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1635 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1636 u64 *tmr_size); 1637 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1638 struct amdgpu_numa_info *numa_info); 1639 1640 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1641 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1642 void amdgpu_acpi_detect(void); 1643 void amdgpu_acpi_release(void); 1644 #else 1645 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1646 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1647 u64 *tmr_offset, u64 *tmr_size) 1648 { 1649 return -EINVAL; 1650 } 1651 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1652 int xcc_id, 1653 struct amdgpu_numa_info *numa_info) 1654 { 1655 return -EINVAL; 1656 } 1657 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1658 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1659 static inline void amdgpu_acpi_detect(void) { } 1660 static inline void amdgpu_acpi_release(void) { } 1661 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1662 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1663 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1664 u8 dev_state, bool drv_state) { return 0; } 1665 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1666 enum amdgpu_ss ss_state) 1667 { 1668 return 0; 1669 } 1670 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1671 { 1672 return -EINVAL; 1673 } 1674 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1675 #endif 1676 1677 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1678 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1679 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1680 #else 1681 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1682 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1683 #endif 1684 1685 #if defined(CONFIG_DRM_AMD_ISP) 1686 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1687 #endif 1688 1689 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1690 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1691 1692 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1693 pci_channel_state_t state); 1694 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1695 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1696 void amdgpu_pci_resume(struct pci_dev *pdev); 1697 1698 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1699 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1700 1701 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1702 1703 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1704 enum amd_clockgating_state state); 1705 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1706 enum amd_powergating_state state); 1707 1708 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1709 { 1710 return amdgpu_gpu_recovery != 0 && 1711 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1712 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1713 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1714 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1715 } 1716 1717 #include "amdgpu_object.h" 1718 1719 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1720 { 1721 return adev->gmc.tmz_enabled; 1722 } 1723 1724 int amdgpu_in_reset(struct amdgpu_device *adev); 1725 1726 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1727 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1728 extern const struct attribute_group amdgpu_flash_attr_group; 1729 1730 void amdgpu_set_init_level(struct amdgpu_device *adev, 1731 enum amdgpu_init_lvl_id lvl); 1732 1733 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1734 { 1735 u32 status; 1736 int r; 1737 1738 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1739 if (r || PCI_POSSIBLE_ERROR(status)) { 1740 dev_err(adev->dev, "device lost from bus!"); 1741 return -ENODEV; 1742 } 1743 1744 return 0; 1745 } 1746 1747 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1748 enum amdgpu_uid_type type, uint8_t inst, 1749 uint64_t uid); 1750 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1751 enum amdgpu_uid_type type, uint8_t inst); 1752 #endif 1753