drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PG[Why&How]ON DCN314, clearing DPP SW structure without power gating it can cause adouble cursor in full screen with non-native
drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PG[Why&How]ON DCN314, clearing DPP SW structure without power gating it can cause adouble cursor in full screen with non-native scaling.A W/A that clears CURSOR0_CONTROL cursor_enable flag ifdcn10_plane_atomic_power_down is called and DPP power gating is disabled.Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com>Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>Signed-off-by: Alex Hung <alex.hung@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>(cherry picked from commit 645f74f1dc119dad5a2c7bbc05cc315e76883011)Cc: stable@vger.kernel.org
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drm/amd/display: Optimize cursor position updates[why]Updating the cursor enablement register can be a slow operation and accumulateswhen high polling rate cursors cause frequent updates asynchro
drm/amd/display: Optimize cursor position updates[why]Updating the cursor enablement register can be a slow operation and accumulateswhen high polling rate cursors cause frequent updates asynchronously to thecursor position.[how]Since the cursor enable bit is cached there is no need to update theenablement register if there is no change to it. This removes theread-modify-write from the cursor position programming path in HUBP andDPP, leaving only the register writes.Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgReviewed-by: Sung Lee <sung.lee@amd.com>Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>Signed-off-by: Wayne Lin <wayne.lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add hubp cache reset when powergating[Why]When HUBP is power gated, the SW state can get out of sync with thehardware state causing cursor to not be programmed correctly.[How]
drm/amd/display: Add hubp cache reset when powergating[Why]When HUBP is power gated, the SW state can get out of sync with thehardware state causing cursor to not be programmed correctly.[How]Similar to DPP, add a HUBP reset function which is called whereverHUBP is initialized or powergated. This function will clear the cursorposition and attribute cache allowing for proper programming when theHUBP is brought back up.Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgReviewed-by: Sung Lee <sung.lee@amd.com>Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>Signed-off-by: Wayne Lin <wayne.lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE[why & how]Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, sincethose macros are not necessary anymore at the
drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE[why & how]Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, sincethose macros are not necessary anymore at the dpp1 set degamma. Thoseare part of an old implementation.Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove unnecessary files[Why & How]We accidentally upstream unnecessary files. Remove them.Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Wayne Lin <Wayne.Lin@a
drm/amd/display: Remove unnecessary files[Why & How]We accidentally upstream unnecessary files. Remove them.Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Improve registers writeAdd REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write forthe regama lut.Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Rodrigo Siqu
drm/amd/display: Improve registers writeAdd REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write forthe regama lut.Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix uninitialized variables in DCThis fixes 49 UNINIT issues reported by Coverity.Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-
drm/amd/display: Fix uninitialized variables in DCThis fixes 49 UNINIT issues reported by Coverity.Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Toggle additional RCO options in DCN35[Why]With root clock optimization now enabled for DCN35 thereare still RCO registers still not being toggled[How]Add in logic to toggle R
drm/amd/display: Toggle additional RCO options in DCN35[Why]With root clock optimization now enabled for DCN35 thereare still RCO registers still not being toggled[How]Add in logic to toggle RCO registers for DPPCLK,DPSTREAMCLK and DSCCLKReviewed-by: Charlene Liu <charlene.liu@amd.com>Acked-by: Roman Li <roman.li@amd.com>Signed-off-by: Daniel Miess <daniel.miess@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Refactor DPP into a component directory[WHY & HOW]Move all dpp files to a new dpp directory.Reviewed-by: Martin Leung <martin.leung@amd.com>Acked-by: Alex Hung <alex.hung@amd.c
drm/amd/display: Refactor DPP into a component directory[WHY & HOW]Move all dpp files to a new dpp directory.Reviewed-by: Martin Leung <martin.leung@amd.com>Acked-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Revalla Hari Krishna <harikrishna.revalla@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>