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Searched refs:getReg (Results 1 – 25 of 726) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp272 MCRegister OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
295 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
333 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
337 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
338 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
342 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
343 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
348 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
352 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
353 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp64 Register Dst = MI.getOperand(0).getReg(); in splitLoad()
66 Register Base = MI.getOperand(1).getReg(); in splitLoad()
79 BasePlusOffset = B.buildPtrAdd({PtrRB, PtrTy}, Base, Offset).getReg(0); in splitLoad()
83 LoadPartRegs.push_back(LoadPart.getReg(0)); in splitLoad()
100 MergeTyParts.push_back(Unmerge.getReg(i)); in splitLoad()
113 Register Dst = MI.getOperand(0).getReg(); in widenLoad()
115 Register Base = MI.getOperand(1).getReg(); in widenLoad()
129 MergeTyParts.push_back(Unmerge.getReg(i)); in widenLoad()
137 Register Dst = MI.getOperand(0).getReg(); in lowerVccExtToSel()
139 Register Src = MI.getOperand(1).getReg(); in lowerVccExtToSel()
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H A DAMDGPURegisterBankInfo.cpp129 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
130 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
145 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
146 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
157 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
168 Register Reg = Op.getReg(); in applyBank()
320 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
325 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
481 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
507 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
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H A DSIOptimizeExecMasking.cpp123 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
124 return MI.getOperand(0).getReg(); in isCopyFromExec()
138 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
139 return MI.getOperand(1).getReg(); in isCopyToExec()
163 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
164 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
166 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
167 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
179 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
180 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
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H A DAMDGPULegalizerInfo.cpp601 const LLT PointerTy = MRI.getType(MO.getReg()); in castBufferRsrcFromV4I32()
619 B.buildExtractVectorElementConstant(S32, VectorReg, I).getReg(0); in castBufferRsrcFromV4I32()
650 PointerParts.push_back(Unmerged.getReg(I)); in castBufferRsrcToV4I32()
651 return B.buildBuildVector(VectorTy, PointerParts).getReg(0); in castBufferRsrcToV4I32()
653 Register Scalar = B.buildPtrToInt(ScalarTy, Pointer).getReg(0); in castBufferRsrcToV4I32()
654 return B.buildBitcast(VectorTy, Scalar).getReg(0); in castBufferRsrcToV4I32()
661 const LLT PointerTy = B.getMRI()->getType(MO.getReg()); in castBufferRsrcArgToV4I32()
665 MO.setReg(castBufferRsrcToV4I32(MO.getReg(), B)); in castBufferRsrcArgToV4I32()
2267 return B.buildUnmerge(S32, Dst).getReg(1); in getSegmentAperture()
2299 B.buildConstant(LLT::scalar(64), Offset).getReg(0)); in getSegmentAperture()
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H A DAMDGPUGlobalISelUtils.cpp50 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset))) in getBaseWithConstantOffset()
51 return std::pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
54 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset)))) in getBaseWithConstantOffset()
55 return std::pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
67 if (mi_match(Def->getOperand(1).getReg(), MRI, in getBaseWithConstantOffset()
71 return std::pair(Base->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
74 return std::pair(Base->getOperand(0).getReg(), Offset); in getBaseWithConstantOffset()
95 S32S64LaneMask.insert(MI.getOperand(3).getReg()); in initLaneMaskIntrinsics()
96 S32S64LaneMask.insert(MI.getOperand(0).getReg()); in initLaneMaskIntrinsics()
101 S32S64LaneMask.insert(MI.getOperand(0).getReg()); in initLaneMaskIntrinsics()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp157 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in tryToReduceVL()
189 SrcVL.ChangeToRegister(VL.getReg(), false); in tryToReduceVL()
205 MachineInstr *Def = MRI->getVRegDef(VL.getReg()); in getConstant()
207 Def->getOperand(1).getReg() != RISCV::X0) in getConstant()
239 MachineInstr *Def = MRI->getVRegDef(VL.getReg()); in convertToVLMAX()
249 Def = MRI->getVRegDef(Def->getOperand(1).getReg()); in convertToVLMAX()
253 Def = MRI->getVRegDef(Def->getOperand(1).getReg()); in convertToVLMAX()
275 while (MaskDef->isCopy() && MaskDef->getOperand(1).getReg().isVirtual()) in isAllOnesMask()
276 MaskDef = MRI->getVRegDef(MaskDef->getOperand(1).getReg()); in isAllOnesMask()
373 if (!isAllOnesMask(MRI->getVRegDef(MI.getOperand(4).getReg()))) in convertAllOnesVMergeToVMv()
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H A DRISCVFoldMemOffset.cpp116 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
119 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
124 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
127 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
132 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
135 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
140 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
143 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
152 if (User.getOperand(1).getReg() == Reg) in foldOffset()
154 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp99 return MIB.buildSub(Ty, Base, Ctlz).getReg(0); in buildLogBase2()
233 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
234 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
238 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
239 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
247 Register DstOp = MI.getOperand(0).getReg(); in matchFreezeOfSingleMaybePoisonOperand()
248 Register OrigOp = MI.getOperand(1).getReg(); in matchFreezeOfSingleMaybePoisonOperand()
274 if (isGuaranteedNotToBeUndefOrPoison(Operand.getReg(), MRI)) in matchFreezeOfSingleMaybePoisonOperand()
297 Register MaybePoisonOperandReg = MaybePoisonOperand->getReg(); in matchFreezeOfSingleMaybePoisonOperand()
308 Freeze.getReg(0)); in matchFreezeOfSingleMaybePoisonOperand()
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H A DGISelValueTracking.cpp59 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
80 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
229 computeKnownBitsImpl(MO.getReg(), Known2, APInt(1, 1), Depth + 1); in computeKnownBitsImpl()
241 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, APInt(1, 1), in computeKnownBitsImpl()
271 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
308 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
310 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
316 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
318 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
328 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
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H A DCombinerHelperVectorOps.cpp37 Register Dst = Extract->getReg(0); in matchExtractVectorElement()
93 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
130 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithDifferentIndices()
170 if (!MRI.hasOneNonDBGUse(Build->getReg(0)) || in matchExtractVectorElementWithBuildVector()
179 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithBuildVector()
190 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithBuildVectorTrunc()
224 if (!MRI.hasOneNonDBGUse(Build->getReg(0)) || in matchExtractVectorElementWithBuildVectorTrunc()
240 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithBuildVectorTrunc()
300 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithShuffleVector()
346 Register Dst = Insert->getReg(0); in matchInsertVectorElementOOB()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp69 Register Src1 = MI.getOperand(1).getReg(); in matchExtractVecEltPairwiseAdd()
70 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd()
71 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
88 Register Src1Op1 = FAddMI->getOperand(1).getReg(); in matchExtractVecEltPairwiseAdd()
89 Register Src1Op2 = FAddMI->getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd()
100 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd()
103 std::get<2>(MatchInfo) = Other->getOperand(0).getReg(); in matchExtractVecEltPairwiseAdd()
121 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
140 Register LHS = MI.getOperand(1).getReg(); in matchAArch64MulConstCombine()
141 Register RHS = MI.getOperand(2).getReg(); in matchAArch64MulConstCombine()
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H A DAArch64PostLegalizerLowering.cpp157 Register Dst = MI.getOperand(0).getReg(); in matchREV()
158 Register Src = MI.getOperand(1).getReg(); in matchREV()
194 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
199 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
200 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
215 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
220 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
221 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
231 Register Dst = MI.getOperand(0).getReg(); in matchZip()
236 Register V1 = MI.getOperand(1).getReg(); in matchZip()
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H A DAArch64PreLegalizerCombiner.cpp51 Register DstReg = MI.getOperand(0).getReg(); in matchFConstantToConstant()
68 MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt()); in applyFConstantToConstant()
83 Register LHS = MI.getOperand(2).getReg(); in matchICmpRedundantTrunc()
88 Register RHS = MI.getOperand(3).getReg(); in matchICmpRedundantTrunc()
116 MI.getOperand(3).setReg(WideZero.getReg(0)); in applyICmpRedundantTrunc()
153 Register Dst = MI.getOperand(0).getReg(); in matchFoldGlobalOffset()
159 UseInstr.getOperand(2).getReg(), MRI); in matchFoldGlobalOffset()
222 Register Dst = MI.getOperand(0).getReg(); in applyFoldGlobalOffset()
241 MachineInstr *I1 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in matchExtAddvToUdotAddv()
242 Register DstReg = MI.getOperand(0).getReg(); in matchExtAddvToUdotAddv()
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H A DAArch64RegisterBankInfo.cpp264 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
285 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
325 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
377 auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg()); in applyMappingImpl()
378 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
379 MI.getOperand(2).setReg(Ext.getReg(0)); in applyMappingImpl()
384 assert(MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() < 32 && in applyMappingImpl()
389 auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in applyMappingImpl()
393 Builder.buildConstant(LLT::scalar(32), CstVal.sext(32)).getReg(0); in applyMappingImpl()
395 ConstReg = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(1).getReg()) in applyMappingImpl()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h38 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); } in getReg() function
87 Register getPointerReg() const { return getOperand(1).getReg(); } in getPointerReg()
108 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg()
110 Register getWritebackReg() const { return getOperand(1).getReg(); } in getWritebackReg()
112 Register getBaseReg() const { return getOperand(2).getReg(); } in getBaseReg()
114 Register getOffsetReg() const { return getOperand(3).getReg(); } in getOffsetReg()
168 Register getWritebackReg() const { return getOperand(0).getReg(); } in getWritebackReg()
170 Register getValueReg() const { return getOperand(1).getReg(); } in getValueReg()
172 Register getBaseReg() const { return getOperand(2).getReg(); } in getBaseReg()
174 Register getOffsetReg() const { return getOperand(3).getReg(); } in getOffsetReg()
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H A DLegalizationArtifactCombiner.h67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
68 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
126 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
127 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
143 SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0); in tryCombineZExt()
145 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineZExt()
201 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
202 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineSExt()
214 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineSExt()
266 Register DstReg = MI.getOperand(0).getReg(); in tryCombineTrunc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp216 Register Reg = Op->getReg(); in getVRegDefOrNull()
275 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
276 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
283 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
284 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
359 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
367 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
403 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
410 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
428 PrimedAccPHI->getOperand(0).getReg(), false), in convertUnprimedAccPHIs()
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H A DPPCMacroFusion.cpp77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
123 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8)) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() ! in checkOpConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp239 if (MI.getOperand(1).getReg() != AArch64::WZR) in visitORR()
242 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR()
257 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
259 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
275 CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
278 TII->get(AArch64::FMOVSWr), SrcMI->getOperand(0).getReg()) in visitORR()
285 Register DefReg = MI.getOperand(0).getReg(); in visitORR()
286 Register SrcReg = MI.getOperand(2).getReg(); in visitORR()
297 if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) in visitCSEL()
306 .addReg(MI.getOperand(0).getReg(), RegState::Define) in visitCSEL()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp174 auto Dest = TRI.regunits(CopyOperands->Destination->getReg().asMCReg()); in invalidateRegister()
175 auto Src = TRI.regunits(CopyOperands->Source->getReg().asMCReg()); in invalidateRegister()
207 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in clobberRegUnit()
208 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in clobberRegUnit()
273 Register Src = CopyOperands->Source->getReg(); in trackSrcUsers()
304 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in trackCopy()
305 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in trackCopy()
359 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailBackwardCopy()
360 Register AvailDef = CopyOperands->Destination->getReg(); in findAvailBackwardCopy()
389 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp95 printRegName(O, Reg.getReg()); in printInst()
103 printRegName(O, Reg.getReg()); in printInst()
111 printRegName(O, Reg.getReg()); in printInst()
119 printRegName(O, Reg.getReg()); in printInst()
137 printRegName(O, Dst.getReg()); in printInst()
139 printRegName(O, MO1.getReg()); in printInst()
142 printRegName(O, MO2.getReg()); in printInst()
159 printRegName(O, Dst.getReg()); in printInst()
161 printRegName(O, MO1.getReg()); in printInst()
178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp197 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
232 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
242 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
255 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
262 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
276 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
277 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
285 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
286 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
295 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp76 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
108 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
118 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
119 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenOn01()
130 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn001()
131 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
132 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) { in shortenOn001()
156 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenFPConv()
157 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenFPConv()
182 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
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