Lines Matching refs:getReg
64 Register Dst = MI.getOperand(0).getReg(); in splitLoad()
66 Register Base = MI.getOperand(1).getReg(); in splitLoad()
79 BasePlusOffset = B.buildPtrAdd({PtrRB, PtrTy}, Base, Offset).getReg(0); in splitLoad()
83 LoadPartRegs.push_back(LoadPart.getReg(0)); in splitLoad()
100 MergeTyParts.push_back(Unmerge.getReg(i)); in splitLoad()
113 Register Dst = MI.getOperand(0).getReg(); in widenLoad()
115 Register Base = MI.getOperand(1).getReg(); in widenLoad()
129 MergeTyParts.push_back(Unmerge.getReg(i)); in widenLoad()
137 Register Dst = MI.getOperand(0).getReg(); in lowerVccExtToSel()
139 Register Src = MI.getOperand(1).getReg(); in lowerVccExtToSel()
165 B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)}); in lowerVccExtToSel()
178 return {Lo.getReg(0), Hi.getReg(0)}; in unpackZExt()
185 return {Lo.getReg(0), Hi.getReg(0)}; in unpackSExt()
192 return {Lo.getReg(0), Hi.getReg(0)}; in unpackAExt()
199 auto [Val0, Val1] = unpackAExt(MI.getOperand(1).getReg()); in lowerUnpackBitShift()
200 auto [Amt0, Amt1] = unpackAExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
201 Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0); in lowerUnpackBitShift()
202 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
206 auto [Val0, Val1] = unpackZExt(MI.getOperand(1).getReg()); in lowerUnpackBitShift()
207 auto [Amt0, Amt1] = unpackZExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
208 Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0); in lowerUnpackBitShift()
209 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
213 auto [Val0, Val1] = unpackSExt(MI.getOperand(1).getReg()); in lowerUnpackBitShift()
214 auto [Amt0, Amt1] = unpackSExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
215 Lo = B.buildAShr(SgprRB_S32, Val0, Amt0).getReg(0); in lowerUnpackBitShift()
216 Hi = B.buildAShr(SgprRB_S32, Val1, Amt1).getReg(0); in lowerUnpackBitShift()
222 B.buildBuildVectorTrunc(MI.getOperand(0).getReg(), {Lo, Hi}); in lowerUnpackBitShift()
234 Register Dst = MI.getOperand(0).getReg(); in lowerV_BFE()
240 Register Src = MI.getOperand(FirstOpnd).getReg(); in lowerV_BFE()
241 Register LSBit = MI.getOperand(FirstOpnd + 1).getReg(); in lowerV_BFE()
242 Register Width = MI.getOperand(FirstOpnd + 2).getReg(); in lowerV_BFE()
265 Register SHRSrcLo = UnmergeSHRSrc.getReg(0); in lowerV_BFE()
266 Register SHRSrcHi = UnmergeSHRSrc.getReg(1); in lowerV_BFE()
293 Register DstReg = MI.getOperand(0).getReg(); in lowerS_BFE()
297 Register Src = MI.getOperand(FirstOpnd).getReg(); in lowerS_BFE()
298 Register LSBit = MI.getOperand(FirstOpnd + 1).getReg(); in lowerS_BFE()
299 Register Width = MI.getOperand(FirstOpnd + 2).getReg(); in lowerS_BFE()
321 B.buildCopy(DstReg, S_BFE->getOperand(0).getReg()); in lowerS_BFE()
326 Register Dst = MI.getOperand(0).getReg(); in lowerSplitTo32()
330 auto Op1 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(1).getReg()); in lowerSplitTo32()
331 auto Op2 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(2).getReg()); in lowerSplitTo32()
335 B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(0), Op2.getReg(0)}, Flags); in lowerSplitTo32()
337 B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(1), Op2.getReg(1)}, Flags); in lowerSplitTo32()
343 Register Dst = MI.getOperand(0).getReg(); in lowerSplitTo32Select()
348 auto Op2 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(2).getReg()); in lowerSplitTo32Select()
349 auto Op3 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(3).getReg()); in lowerSplitTo32Select()
350 Register Cond = MI.getOperand(1).getReg(); in lowerSplitTo32Select()
353 B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(0), Op3.getReg(0), Flags); in lowerSplitTo32Select()
355 B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(1), Op3.getReg(1), Flags); in lowerSplitTo32Select()
362 auto Op1 = B.buildUnmerge(VgprRB_S32, MI.getOperand(1).getReg()); in lowerSplitTo32SExtInReg()
367 auto Freeze = B.buildFreeze(VgprRB_S32, Op1.getReg(0)); in lowerSplitTo32SExtInReg()
370 Lo = Freeze.getReg(0); in lowerSplitTo32SExtInReg()
373 Lo = B.buildSExtInReg(VgprRB_S32, Freeze, Amt).getReg(0); in lowerSplitTo32SExtInReg()
377 Hi = B.buildAShr(VgprRB_S32, Lo, SignExtCst).getReg(0); in lowerSplitTo32SExtInReg()
380 Lo = Op1.getReg(0); in lowerSplitTo32SExtInReg()
381 Hi = B.buildSExtInReg(VgprRB_S32, Op1.getReg(1), Amt - 32).getReg(0); in lowerSplitTo32SExtInReg()
384 B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi}); in lowerSplitTo32SExtInReg()
398 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in lower()
405 B.buildSelect(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), True, in lower()
413 const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); in lower()
423 Hi = B.buildAShr({RB, S32}, MI.getOperand(1).getReg(), ShiftAmt); in lower()
434 B.buildMergeLikeInstr(MI.getOperand(0).getReg(), in lower()
435 {MI.getOperand(1).getReg(), Hi}); in lower()
441 B.buildConstant(MI.getOperand(0).getReg(), ConstVal); in lower()
447 Register Src = MI.getOperand(1).getReg(); in lower()
456 auto AndLo = B.buildAnd(VgprRB_S32, Src64.getReg(0), One); in lower()
458 auto AndHi = B.buildAnd(VgprRB_S32, Src64.getReg(1), Zero); in lower()
466 B.buildICmp(CmpInst::ICMP_NE, MI.getOperand(0).getReg(), BoolSrc, Zero); in lower()
481 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in lower()
515 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in lower()
724 Register Reg = Op.getReg(); in applyMappingDst()
843 Register Reg = Op.getReg(); in applyMappingSrc()
855 Op.setReg(CopyVcc_Scc.getReg(0)); in applyMappingSrc()
905 Op.setReg(CopyToVgpr.getReg(0)); in applyMappingSrc()
922 Op.setReg(CopyToVgpr.getReg(0)); in applyMappingSrc()
932 Op.setReg(Aext.getReg(0)); in applyMappingSrc()
944 Op.setReg(BoolInReg.getReg(0)); in applyMappingSrc()
951 Op.setReg(Sext.getReg(0)); in applyMappingSrc()
958 Op.setReg(Zext.getReg(0)); in applyMappingSrc()
966 Op.setReg(Sext.getReg(0)); in applyMappingSrc()
974 Op.setReg(Zext.getReg(0)); in applyMappingSrc()
984 Register Dst = MI.getOperand(0).getReg(); in applyMappingPHI()
995 Register UseReg = MI.getOperand(i).getReg(); in applyMappingPHI()
1003 MI.getOperand(i).setReg(NewUse.getReg(0)); in applyMappingPHI()
1036 if (MRI.getRegBankOrNull(MI.getOperand(i).getReg()) != RB) in verifyRegBankOnOperands()
1043 const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); in applyMappingTrivial()
1055 Register Reg = MI.getOperand(i).getReg(); in applyMappingTrivial()
1058 MI.getOperand(i).setReg(Copy.getReg(0)); in applyMappingTrivial()