Lines Matching refs:getReg
161 Register Dst = MI.getOperand(0).getReg(); in matchREV()
162 Register Src = MI.getOperand(1).getReg(); in matchREV()
198 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
203 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
204 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
219 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
224 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
225 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
235 Register Dst = MI.getOperand(0).getReg(); in matchZip()
240 Register V1 = MI.getOperand(1).getReg(); in matchZip()
241 Register V2 = MI.getOperand(2).getReg(); in matchZip()
269 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
273 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
278 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ZeroInt())) in matchDupFromInsertVectorElt()
281 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
282 {InsMI->getOperand(2).getReg()}); in matchDupFromInsertVectorElt()
294 MI.getOperand(1).getReg(), MRI); in matchDupFromBuildVector()
297 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
299 ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), {Reg}); in matchDupFromBuildVector()
352 Register Dst = MI.getOperand(0).getReg(); in matchEXT()
354 Register V1 = MI.getOperand(1).getReg(); in matchEXT()
355 Register V2 = MI.getOperand(2).getReg(); in matchEXT()
409 getIConstantVRegValWithLookThrough(MI.getOperand(3).getReg(), MRI); in matchNonConstInsert()
419 LLT VecTy = MRI.getType(Insert.getReg(0)); in applyNonConstInsert()
440 Register And = Builder.buildAnd(IdxTy, Offset, Mask).getReg(0); in applyNonConstInsert()
442 Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); in applyNonConstInsert()
444 Builder.buildPtrAdd(MRI.getType(StackTemp.getReg(0)), StackTemp, Mul) in applyNonConstInsert()
445 .getReg(0); in applyNonConstInsert()
450 Builder.buildLoad(Insert.getReg(0), StackTemp, PtrInfo, Align(8)); in applyNonConstInsert()
469 Register Dst = MI.getOperand(0).getReg(); in matchINS()
477 Register Left = MI.getOperand(1).getReg(); in matchINS()
478 Register Right = MI.getOperand(2).getReg(); in matchINS()
496 Register Dst = MI.getOperand(0).getReg(); in applyINS()
528 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in matchVAshrLshrImm()
531 return isVShiftRImm(MI.getOperand(2).getReg(), MRI, Ty, Imm); in matchVAshrLshrImm()
666 Register RHS = MI.getOperand(3).getReg(); in matchAdjustICmpImmAndPred()
681 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred()
684 RHS.setReg(Cst->getOperand(0).getReg()); in applyAdjustICmpImmAndPred()
692 Register Src1Reg = MI.getOperand(1).getReg(); in matchDupLane()
694 const LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchDupLane()
748 Register Src1Reg = MI.getOperand(1).getReg(); in applyDupLane()
754 Register DupSrc = MI.getOperand(1).getReg(); in applyDupLane()
760 {Src1Reg, Undef.getReg(0)}) in applyDupLane()
761 .getReg(0); in applyDupLane()
763 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
769 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); in matchScalarizeVectorUnmerge()
780 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); in applyScalarizeVectorUnmerge()
786 B.buildExtractVectorElementConstant(Unmerge.getReg(I), Src1Reg, I); in applyScalarizeVectorUnmerge()
807 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
808 {MI.getOperand(1).getReg()}); in applyBuildVectorToDup()
826 getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI); in getCmpOperandFoldingProfit()
843 getIConstantVRegValWithLookThrough(Def->getOperand(2).getReg(), MRI); in getCmpOperandFoldingProfit()
848 getDefIgnoringCopies(Def->getOperand(1).getReg(), MRI); in getCmpOperandFoldingProfit()
856 LLT Ty = MRI.getType(Def->getOperand(0).getReg()); in getCmpOperandFoldingProfit()
881 Register RHS = MI.getOperand(3).getReg(); in trySwapICmpOperands()
886 Register LHS = MI.getOperand(2).getReg(); in trySwapICmpOperands()
890 return isCMN(Def, Pred, MRI) ? Def->getOperand(2).getReg() : Reg; in trySwapICmpOperands()
906 Register LHS = MI.getOperand(2).getReg(); in applySwapICmpOperands()
907 Register RHS = MI.getOperand(3).getReg(); in applySwapICmpOperands()
933 return MIB.buildNot(DstTy, FCmp).getReg(0); in getVectorFCMP()
938 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
940 .getReg(0); in getVectorFCMP()
945 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
947 .getReg(0); in getVectorFCMP()
952 ? MIB.buildInstr(AArch64::G_FCMGTZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
954 .getReg(0); in getVectorFCMP()
959 ? MIB.buildInstr(AArch64::G_FCMLEZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
961 .getReg(0); in getVectorFCMP()
966 ? MIB.buildInstr(AArch64::G_FCMLTZ, {DstTy}, {LHS}).getReg(0) in getVectorFCMP()
968 .getReg(0); in getVectorFCMP()
979 Register Dst = MI.getOperand(0).getReg(); in matchLowerVectorFCMP()
983 Register LHS = MI.getOperand(2).getReg(); in matchLowerVectorFCMP()
1001 Register Dst = CmpMI.getReg(0); in applyLowerVectorFCMP()
1043 CmpRes = MIB.buildOr(DstTy, Cmp1Dst, Cmp2Dst).getReg(0); in applyLowerVectorFCMP()
1046 CmpRes = MIB.buildNot(DstTy, CmpRes).getReg(0); in applyLowerVectorFCMP()
1054 Register DstReg = MI.getOperand(0).getReg(); in matchFormTruncstore()
1078 Register DstReg = MI.getOperand(0).getReg(); in matchVectorSextInReg()
1098 if (!MRI.use_nodbg_empty(Unmerge.getReg(1))) in matchUnmergeExtToUnmerge()
1101 LLT DstTy = MRI.getType(Unmerge.getReg(0)); in matchUnmergeExtToUnmerge()
1109 Register ExtSrc1 = Ext->getOperand(1).getReg(); in matchUnmergeExtToUnmerge()
1110 Register ExtSrc2 = Ext->getOperand(2).getReg(); in matchUnmergeExtToUnmerge()
1112 getIConstantVRegValWithLookThrough(Ext->getOperand(3).getReg(), MRI); in matchUnmergeExtToUnmerge()
1128 Register Dst1 = MI.getOperand(0).getReg(); in applyUnmergeExtToUnmerge()
1129 MI.getOperand(0).setReg(MI.getOperand(1).getReg()); in applyUnmergeExtToUnmerge()
1142 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtMulToMULL()
1143 MachineInstr *I1 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in matchExtMulToMULL()
1144 MachineInstr *I2 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in matchExtMulToMULL()
1152 (MRI.getType(I1->getOperand(0).getReg()).getScalarSizeInBits() == in matchExtMulToMULL()
1153 MRI.getType(I1->getOperand(1).getReg()).getScalarSizeInBits() * 2) && in matchExtMulToMULL()
1154 (MRI.getType(I2->getOperand(0).getReg()).getScalarSizeInBits() == in matchExtMulToMULL()
1155 MRI.getType(I2->getOperand(1).getReg()).getScalarSizeInBits() * 2)) { in matchExtMulToMULL()
1172 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in applyExtMulToMULL()
1173 MachineInstr *I1 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in applyExtMulToMULL()
1174 MachineInstr *I2 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in applyExtMulToMULL()
1181 (MRI.getType(I1->getOperand(0).getReg()).getScalarSizeInBits() == in applyExtMulToMULL()
1182 MRI.getType(I1->getOperand(1).getReg()).getScalarSizeInBits() * 2) && in applyExtMulToMULL()
1183 (MRI.getType(I2->getOperand(0).getReg()).getScalarSizeInBits() == in applyExtMulToMULL()
1184 MRI.getType(I2->getOperand(1).getReg()).getScalarSizeInBits() * 2)) { in applyExtMulToMULL()
1189 {MI.getOperand(0).getReg()}, in applyExtMulToMULL()
1190 {I1->getOperand(1).getReg(), I2->getOperand(1).getReg()}); in applyExtMulToMULL()