| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
9 /// This file implements the RegisterBank class.
12 #include "llvm/CodeGen/RegisterBank.h"
23 bool RegisterBank::verify(const RegisterBankInfo &RBI,
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in verify()
56 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in verify()
61 "ID does not uniquely identify a RegisterBank"); in verify()
66 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in covers()
71 void RegisterBank in isValid()
25 RegisterBank::RegisterBank(unsigned ID, const char *Name, RegisterBank() function in RegisterBank
[all...] |
| H A D | RegisterBankInfo.cpp | 56 RegisterBankInfo::RegisterBankInfo(const RegisterBank **RegBanks, in RegisterBankInfo()
73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
83 const RegisterBank *
94 if (auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank)) in getRegBank()
111 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
124 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints()
139 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister()
195 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
199 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank;
67 const RegisterBank &RegBank) in PartialMapping()
389 const RegisterBank **RegBanks;
426 RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks,
440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank()
472 const RegisterBank &RegBank) const;
480 const RegisterBank &RegBank) const;
553 const RegisterBank *
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
[all …]
|
| H A D | RegisterBank.h | 29 class RegisterBank {
40 constexpr RegisterBank(unsigned ID, const char *Name, in RegisterBank() function
67 LLVM_ABI bool operator==(const RegisterBank &OtherRB) const;
68 bool operator!=(const RegisterBank &OtherRB) const {
85 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankSelect.cpp | 84 const RegisterBank *SgprRB;
85 const RegisterBank *VgprRB;
86 const RegisterBank *VccRB;
112 const RegisterBank *getRegBankToAssign(Register Reg) { in getRegBankToAssign()
130 const RegisterBank *RB) { in reAssignRegBankOnDef()
169 const RegisterBank *RB) { in constrainRegBankUse()
262 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg); in runOnMachineFunction()
284 const RegisterBank *RB = RBSHelper.getRegBankToAssign(UseReg); in runOnMachineFunction()
|
| H A D | AMDGPURegisterBanks.td | 9 def SGPRRegBank : RegisterBank<"SGPR",
13 def VGPRRegBank : RegisterBank<"VGPR",
18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
20 def AGPRRegBank : RegisterBank <"AGPR",
|
| H A D | AMDGPURegisterBankInfo.h | 168 bool isDivergentRegBank(const RegisterBank *RB) const override;
170 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
174 const RegisterBank *CurBank = nullptr) const override;
176 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
|
| H A D | AMDGPURegBankLegalizeHelper.h | 35 const RegisterBank *SgprRB;
36 const RegisterBank *VgprRB;
37 const RegisterBank *VccRB;
95 const RegisterBank *getRegBankFromID(RegBankLLTMappingApplyID ID);
|
| H A D | AMDGPURegBankLegalize.cpp | 101 const RegisterBank *SgprRB;
102 const RegisterBank *VgprRB;
103 const RegisterBank *VccRB;
119 const RegisterBank *RB = MRI.getRegBankOrNull(Reg); in isLaneMask()
247 const RegisterBank *RB = MRI.getRegBankOrNull(Reg); in getAnySgprS1()
|
| H A D | AMDGPURegisterBankInfo.cpp | 103 const RegisterBank *NewBank;
108 MachineRegisterInfo &MRI_, const RegisterBank *RB) in ApplyRegBankMapping()
131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
172 const RegisterBank *RB = NewBank; in applyBank()
221 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank()
226 bool AMDGPURegisterBankInfo::isDivergentRegBank(const RegisterBank *RB) const { in isDivergentRegBank()
230 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, in copyCost()
231 const RegisterBank &Src, in copyCost()
263 const RegisterBank *CurBank) const { in getBreakDownCost()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBanks.td | 15 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
17 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
19 def VECRegBank : RegisterBank<"VEC", [VSRC]>;
21 def CRRegBank : RegisterBank<"CR", [CRRC]>;
|
| H A D | PPCRegisterBankInfo.cpp | 32 const RegisterBank &
210 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
211 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 30 class RegisterBank { class
45 RegisterBank(const Record &TheDef, unsigned NumModeIds) in RegisterBank() function in __anondde7a8760111::RegisterBank
115 ArrayRef<RegisterBank> Banks);
117 ArrayRef<RegisterBank> Banks);
119 ArrayRef<RegisterBank> Banks);
133 ArrayRef<RegisterBank> Banks) { in emitHeader()
151 raw_ostream &OS, const StringRef TargetName, ArrayRef<RegisterBank> Banks) { in emitBaseClassDefinition()
221 raw_ostream &OS, StringRef TargetName, ArrayRef<RegisterBank> Banks) { in emitBaseClassImplementation()
392 std::vector<RegisterBank> Banks; in run()
395 RegisterBank Bank(*V, CGH.getNumModeIds()); in run()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.h | 66 unsigned ValLength, const RegisterBank &RB);
149 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
152 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
|
| H A D | AArch64RegisterBankInfo.cpp | 57 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
67 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
220 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
221 const RegisterBank &B, in copyCost()
241 const RegisterBank &
723 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
724 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
748 const RegisterBank &DstRB = in getInstrMapping()
750 const RegisterBank &SrcRB = in getInstrMapping()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
19 def PSRRegBank : RegisterBank<"PSR", [RFP32, RFP64, RFP80]>;
|
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;
16 def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;
19 def CCRegBank : RegisterBank<"CC", [CCR]>;
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 31 class RegisterBank; variable
44 const RegisterBank *RegBank;
52 using Name2RegBankMap = StringMap<const RegisterBank *>;
150 const RegisterBank *getRegBank(StringRef Name);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBanks.td | 12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/ |
| H A D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
12 class RegisterBank<string name, list<RegisterClass> classes> {
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBanks.td | 12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterBanks.td | 12 def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
13 def IDRegBank : RegisterBank<"IDBank", [ID]>;
|
| H A D | SPIRVRegisterBankInfo.cpp | 28 const RegisterBank &
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
77 unsigned getPtrLoadStoreOp(const LLT &Ty, const RegisterBank &RB,
134 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
176 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
217 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
266 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank); in selectDebugInstr()
285 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
289 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
454 const RegisterBank &RB, in getPtrLoadStoreOp()
473 const RegisterBank &RB, in getLoadStoreOp()
[all …]
|