14824e7fdSDimitry Andric//=- X86RegisterBank.td - Describe the X86 Banks -------------*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// 100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric/// General Purpose Registers: RAX, RCX,... 130b57cec5SDimitry Andricdef GPRRegBank : RegisterBank<"GPR", [GR64]>; 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric/// Floating Point/Vector Registers 160b57cec5SDimitry Andricdef VECRRegBank : RegisterBank<"VECR", [VR512]>; 17*0fca6ea1SDimitry Andric 18*0fca6ea1SDimitry Andric/// Pseudo Registers: RFP80 19*0fca6ea1SDimitry Andricdef PSRRegBank : RegisterBank<"PSR", [RFP32, RFP64, RFP80]>; 20