1*0b57cec5SDimitry Andric//=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// 10*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andricdef GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>; 13*0b57cec5SDimitry Andricdef FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>; 14