1e8d8bef9SDimitry Andric//===-- PPCRegisterBanks.td - Describe the PPC Banks -------*- tablegen -*-===// 2e8d8bef9SDimitry Andric// 3e8d8bef9SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric// 7e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric/// 9e8d8bef9SDimitry Andric/// \file 10e8d8bef9SDimitry Andric/// Define the PPC register banks used for GlobalISel. 11e8d8bef9SDimitry Andric/// 12e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 13e8d8bef9SDimitry Andric 14e8d8bef9SDimitry Andric/// General Purpose Registers 15bdd1243dSDimitry Andricdef GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>; 16bdd1243dSDimitry Andric/// Floating point Registers 17bdd1243dSDimitry Andricdef FPRRegBank : RegisterBank<"FPR", [VSSRC]>; 18*06c3fb27SDimitry Andric/// Vector Registers 19*06c3fb27SDimitry Andricdef VECRegBank : RegisterBank<"VEC", [VSRC]>; 20bdd1243dSDimitry Andric/// Condition Registers 21bdd1243dSDimitry Andricdef CRRegBank : RegisterBank<"CR", [CRRC]>; 22