10b57cec5SDimitry Andric//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// 100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric/// General Purpose Registers: W, X. 13fe6060f1SDimitry Andricdef GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>; 140b57cec5SDimitry Andric 15*0fca6ea1SDimitry Andric/// Floating Point, Vector, Scalable Vector Registers: B, H, S, D, Q, Z. 16*0fca6ea1SDimitry Andricdef FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>; 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric/// Conditional register: NZCV. 190b57cec5SDimitry Andricdef CCRegBank : RegisterBank<"CC", [CCR]>; 20