181ad6265SDimitry Andric //==-- llvm/CodeGen/RegisterBank.h - Register Bank ---------------*- C++ -*-==// 281ad6265SDimitry Andric // 381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric // 781ad6265SDimitry Andric //===----------------------------------------------------------------------===// 881ad6265SDimitry Andric // 981ad6265SDimitry Andric /// \file This file declares the API of register banks. 1081ad6265SDimitry Andric // 1181ad6265SDimitry Andric //===----------------------------------------------------------------------===// 1281ad6265SDimitry Andric 1381ad6265SDimitry Andric #ifndef LLVM_CODEGEN_REGISTERBANK_H 1481ad6265SDimitry Andric #define LLVM_CODEGEN_REGISTERBANK_H 1581ad6265SDimitry Andric 16*5f757f3fSDimitry Andric #include <cstdint> 1781ad6265SDimitry Andric 1881ad6265SDimitry Andric namespace llvm { 1981ad6265SDimitry Andric // Forward declarations. 2081ad6265SDimitry Andric class RegisterBankInfo; 2181ad6265SDimitry Andric class raw_ostream; 2281ad6265SDimitry Andric class TargetRegisterClass; 2381ad6265SDimitry Andric class TargetRegisterInfo; 2481ad6265SDimitry Andric 2581ad6265SDimitry Andric /// This class implements the register bank concept. 2681ad6265SDimitry Andric /// Two instances of RegisterBank must have different ID. 2781ad6265SDimitry Andric /// This property is enforced by the RegisterBankInfo class. 2881ad6265SDimitry Andric class RegisterBank { 2981ad6265SDimitry Andric private: 3081ad6265SDimitry Andric unsigned ID; 31*5f757f3fSDimitry Andric unsigned NumRegClasses; 3281ad6265SDimitry Andric const char *Name; 33*5f757f3fSDimitry Andric const uint32_t *CoveredClasses; 3481ad6265SDimitry Andric 3581ad6265SDimitry Andric /// Only the RegisterBankInfo can initialize RegisterBank properly. 3681ad6265SDimitry Andric friend RegisterBankInfo; 3781ad6265SDimitry Andric 3881ad6265SDimitry Andric public: 39*5f757f3fSDimitry Andric constexpr RegisterBank(unsigned ID, const char *Name, 40*5f757f3fSDimitry Andric const uint32_t *CoveredClasses, unsigned NumRegClasses) 41*5f757f3fSDimitry Andric : ID(ID), NumRegClasses(NumRegClasses), Name(Name), 42*5f757f3fSDimitry Andric CoveredClasses(CoveredClasses) {} 4381ad6265SDimitry Andric 4481ad6265SDimitry Andric /// Get the identifier of this register bank. 4581ad6265SDimitry Andric unsigned getID() const { return ID; } 4681ad6265SDimitry Andric 4781ad6265SDimitry Andric /// Get a user friendly name of this register bank. 4881ad6265SDimitry Andric /// Should be used only for debugging purposes. 4981ad6265SDimitry Andric const char *getName() const { return Name; } 5081ad6265SDimitry Andric 5181ad6265SDimitry Andric /// Check if this register bank is valid. In other words, 5281ad6265SDimitry Andric /// if it has been properly constructed. 5381ad6265SDimitry Andric /// 5481ad6265SDimitry Andric /// \note This method does not check anything when assertions are disabled. 5581ad6265SDimitry Andric /// 5681ad6265SDimitry Andric /// \return True is the check was successful. 5706c3fb27SDimitry Andric bool verify(const RegisterBankInfo &RBI, const TargetRegisterInfo &TRI) const; 5881ad6265SDimitry Andric 5981ad6265SDimitry Andric /// Check whether this register bank covers \p RC. 6081ad6265SDimitry Andric /// In other words, check if this register bank fully covers 6181ad6265SDimitry Andric /// the registers that \p RC contains. 6281ad6265SDimitry Andric bool covers(const TargetRegisterClass &RC) const; 6381ad6265SDimitry Andric 6481ad6265SDimitry Andric /// Check whether \p OtherRB is the same as this. 6581ad6265SDimitry Andric bool operator==(const RegisterBank &OtherRB) const; 6681ad6265SDimitry Andric bool operator!=(const RegisterBank &OtherRB) const { 6781ad6265SDimitry Andric return !this->operator==(OtherRB); 6881ad6265SDimitry Andric } 6981ad6265SDimitry Andric 7081ad6265SDimitry Andric /// Dump the register mask on dbgs() stream. 7181ad6265SDimitry Andric /// The dump is verbose. 7281ad6265SDimitry Andric void dump(const TargetRegisterInfo *TRI = nullptr) const; 7381ad6265SDimitry Andric 7481ad6265SDimitry Andric /// Print the register mask on OS. 7581ad6265SDimitry Andric /// If IsForDebug is false, then only the name of the register bank 7681ad6265SDimitry Andric /// is printed. Otherwise, all the fields are printing. 7781ad6265SDimitry Andric /// TRI is then used to print the name of the register classes that 7881ad6265SDimitry Andric /// this register bank covers. 7981ad6265SDimitry Andric void print(raw_ostream &OS, bool IsForDebug = false, 8081ad6265SDimitry Andric const TargetRegisterInfo *TRI = nullptr) const; 8181ad6265SDimitry Andric }; 8281ad6265SDimitry Andric 8381ad6265SDimitry Andric inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) { 8481ad6265SDimitry Andric RegBank.print(OS); 8581ad6265SDimitry Andric return OS; 8681ad6265SDimitry Andric } 8781ad6265SDimitry Andric } // End namespace llvm. 8881ad6265SDimitry Andric 8981ad6265SDimitry Andric #endif 90