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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
H A Dsja1000.txt5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
27 <0x1> : normal output mode (default)
28 <0x2> : test output mode
29 <0x3> : clock output mode
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-t
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H A Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsa8775p-ride.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "sa8775p-pmics.dtsi"
28 stdout-path = "serial0:115200n8";
33 regulators-0 {
34 compatible = "qcom,pmm8654au-rpmh-regulators";
35 qcom,pmic-id = "a";
38 regulator-name = "vreg_s4a";
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H A Dsm8250.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
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H A Dsm8450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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H A Dx1e80100.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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/freebsd/sys/dev/igc/
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
228 #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
278 /* 1000/H is not supported, nor spec-compliant. */
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/freebsd/sys/dev/ixl/
H A Dixl_pf_main.c3 Copyright (c) 2013-2018, Intel Corporation
108 "Tx",
115 "CL108 RS-FEC",
116 "CL74 FC-FEC/BASE-R",
127 * ixl_set_state - Set the specified state
141 * ixl_clear_state - Clear the specified state
155 * ixl_test_state - Test the specified state
170 * ixl_testandset_state - Test and set the specified state
193 u8 oem_ver = (u8)(hw->nvm.oem_ver >> 24); in ixl_nvm_version_str()
194 u16 oem_build = (u16)((hw->nvm.oem_ver >> 16) & 0xFFFF); in ixl_nvm_version_str()
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/freebsd/sys/dev/liquidio/base/
H A Dlio_config.h41 /*--------------------------CONFIG VALUES------------------------*/
90 #define LIO_CN23XX_MAX_INPUT_JABBER (LIO_CN23XX_PKI_MAX_FRAME_SIZE - \
101 /* Macros to get octeon config params */
102 #define LIO_GET_IQ_CFG(cfg) ((cfg)->iq)
103 #define LIO_GET_IQ_MAX_Q_CFG(cfg) ((cfg)->iq.max_iqs)
104 #define LIO_GET_IQ_INSTR_TYPE_CFG(cfg) ((cfg)->iq.instr_type)
106 #define LIO_GET_IQ_INTR_PKT_CFG(cfg) ((cfg)->iq.iq_intr_pkt)
108 #define LIO_GET_OQ_MAX_Q_CFG(cfg) ((cfg)->oq.max_oqs)
109 #define LIO_GET_OQ_PKTS_PER_INTR_CFG(cfg) ((cfg)->oq.pkts_per_intr)
110 #define LIO_GET_OQ_REFILL_THRESHOLD_CFG(cfg) ((cfg)->oq.refill_threshold)
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/freebsd/contrib/ntp/libntp/
H A Dicom.c8 #include <config.h>
21 #undef write /* ports/winnt/include/config.h: #define write _write */
38 * Frames begin with a two-octet preamble PR-PR followyd by the
39 * transceiver address RE, controller address TX, control code CN, zero
41 * Since the bus is bidirectional, every octet output is echoed on
43 * format, but with the RE and TX fields interchanged. The CN field is
48 * +------+------+------+------+------+--//--+------+
49 * | PR | PR | RE | TX | CN | DA | FI |
50 * +------+------+------+------+------+--//--+------+
64 * icom_freq(fd, ident, freq) - load radio frequency
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
23 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-geni-qcom.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
17 mini-core.
24 described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
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/freebsd/sys/dev/rl/
H A Dif_rlreg.h1 /*-
2 * Copyright (c) 1997, 1998-2003
16 * 4. Neither the name of the author nor the names of any co-contributors
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
42 /* 0006-0007 reserved */
52 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
53 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
54 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
55 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
57 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
[all …]
/freebsd/sys/dev/e1000/
H A De1000_regs.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
[all …]
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
280 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_spi_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 sc->config.input_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
80 sc->config.input_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
82 /* Output block size */ in qcom_spi_hw_read_controller_transfer_sizes()
86 sc->config.output_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
88 sc->config.output_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
93 sc->config.input_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
94 sc->config.input_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
96 /* Output FIFO size */ in qcom_spi_hw_read_controller_transfer_sizes()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
17 clk_dummy: clock-dummy {
18 compatible = "fixed-clock";
[all …]
H A Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
[all …]
/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-x86_64.pl2 # Copyright 2005-2023 The OpenSSL Project Authors. All Rights Reserved.
19 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
20 # "hand-coded assembler"] doesn't stand for the whole improvement
21 # coefficient. It turned out that eliminating RC4_CHAR from config
24 # RAW or whatever penalties. Once again! The module *requires* config
34 # results in even higher performance gain of 3.3x:-) At least on
35 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
51 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
58 # performance by >30% [unlike P4 32-bit case that is]. But this is
61 # as my IA-64 implementation. On Opteron this resulted in modest 5%
[all …]

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