Lines Matching +full:tx +full:- +full:output +full:- +full:config
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
280 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
281 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
412 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
416 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
424 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
566 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
567 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
589 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
590 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
591 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
592 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
617 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
632 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
633 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
644 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
645 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
646 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
647 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
661 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
662 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
663 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
664 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
755 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
756 #define E1000_RXCW_C 0x20000000 /* Receive config */
757 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
759 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
760 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
864 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
870 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
958 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
959 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
970 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
971 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
983 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
984 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
986 /* 1000BASE-T Control Register */
994 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
1002 /* 1000BASE-T Status Register */
1009 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1010 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1023 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1085 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1146 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1310 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1491 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */