Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
229 #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
279 /* 1000/H is not supported, nor spec-compliant. */
325 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
333 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
346 /* GPY211 - I225 defines */
475 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
476 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
477 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
478 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
503 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
525 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
526 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
527 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
528 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
542 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
543 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
544 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
545 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
631 #define IGC_RXCW_IV 0x08000000 /* Receive config invalid */
632 #define IGC_RXCW_C 0x20000000 /* Receive config */
633 #define IGC_RXCW_SYNCH 0x40000000 /* Receive config synch */
635 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
636 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
706 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
707 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
708 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
709 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
710 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
711 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
712 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
713 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
714 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
715 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
716 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
717 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
718 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
719 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
720 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
721 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
787 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
793 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
853 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
854 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
865 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
866 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
878 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
879 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
881 /* 1000BASE-T Control Register */
889 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
897 /* 1000BASE-T Status Register */
904 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
905 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
918 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1005 #define IGC_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1133 #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1255 #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1261 * of EEE LPI Tx state
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out
1265 * of EEE LPI Tx state
1289 #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */