| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
8 .\" 1. Redistributions of source code must retain the above copyright notice, this
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
80 0x1AE0:0x0042
84 Change the TX queue count to 4 for the gve0 interface:
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| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
10 .\" 1. Redistributions of source code must retain the above copyright
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
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| H A D | iflib.4 | 24 .Xr kenv 1 .
28 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
47 Set the number of RX queues.
48 If zero, the number of RX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,rzv2h-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
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| H A D | renesas,r9a09g057-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
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| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
25 NetCP subsystem(10G or 1G)
26 -----------------------------
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| H A D | intel,ixp4xx-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
27 maxItems: 1
30 queue-rx:
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| H A D | intel,ixp4xx-hss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
23 maxItems: 1
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
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| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
10 * 1. Redistributions of source code must retain the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
57 #define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */
61 #define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */
65 #define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */
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| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
10 * 1. Redistributions of source code must retain the above copyright
36 #define PORT_1 1
96 uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
115 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
116 uint32_t txq_size; /* TX Descriptors Queue Size */
117 uint32_t rxq_size; /* RX Descriptors Queue Size */
118 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
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| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2l-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
20 #address-cells = <1>;
21 #size-cells = <1>;
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| H A D | keystone-k2e-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| H A D | keystone-k2g-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,66ak2g-navss-qm";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 power-domains = <&k2g_pds 0x0018>;
15 clock-names = "nss_vclk";
17 queue-range = <0 0x80>;
22 #address-cells = <1>;
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
82 #define AL_ETH_REV_ID_1 1 /* Alpine V1 Rev 1 */
95 #define AL_ETH_TSO_MSS_MIN_VAL 1
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
114 AL_ETH_TUNNEL_NO_UDP = 1, /* NVGRE / IP over IP */
118 #define AL_ETH_RX_THASH_TABLE_SIZE (1 << 8)
119 #define AL_ETH_RX_FSM_TABLE_SIZE (1 << 7)
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
10 1. Redistributions of source code must retain the above copyright notice,
73 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
74 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
75 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
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| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 1. Redistributions of source code must retain the above copyright
39 * a 3-port store-and-forward switch connected to two independent
40 * "sliver" controllers (port 1 and port 2). You can operate the
233 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1);
238 MODULE_DEPEND(cpsw, ether, 1, 1, 1);
239 MODULE_DEPEND(cpsw, miibus, 1, 1, 1);
249 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
252 { -1, 0 }
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: ISC
16 struct mt7996_dev *dev = phy->dev; in mt7996_init_tx_queues()
21 idx -= MT_TXQ_ID(0); in mt7996_init_tx_queues()
23 if (phy->mt76->band_idx == MT_BAND2) in mt7996_init_tx_queues()
29 return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, in mt7996_init_tx_queues()
39 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
50 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
51 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
52 dev->q_id[(q)] = id; \ in mt7996_dma_config()
59 /* rx queue */ in mt7996_dma_config()
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| /freebsd/sys/dev/neta/ |
| H A D | if_mvnetareg.h | 10 * 1. Redistributions of source code must retain the above copyright
45 #define MVNETA_RX_QNUM_MAX 1
46 /* XXX: Currently multi-queue can be used on the Tx side only */
50 #define MVNETA_TX_QNUM_MAX 1
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
60 #define MVNETA_QUEUE(n) (1 << (n))
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
99 /* Rx DMA Hardware Parser Registers */
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| H A D | if_mvneta.c | 9 * 1. Redistributions of source code must retain the above copyright
111 /* Rx/Tx Queue Control */
166 /* Rx Subroutines */
191 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx)
192 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx)
221 MODULE_DEPEND(mvneta, mdio, 1, 1, 1);
222 MODULE_DEPEND(mvneta, ether, 1, 1, 1);
223 MODULE_DEPEND(mvneta, miibus, 1, 1, 1);
224 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1);
269 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1,
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| /freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/ |
| H A D | rx.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-prph.h"
12 #include "iwl-io.h"
14 #include "iwl-op-mode.h"
15 #include "pcie/iwl-context-info-v2.h"
20 * RX path functions
25 * Rx theory of operation
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| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_hw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
9 * 1. Redistributions of source code must retain the above copyright
66 * for the ESS core - and that includes both the EDMA (ethernet)
69 * AND, it's a placeholder for what the linux ess-edma driver
72 * ess-switch won't be initialised. In that case it defaults
77 * So, for now this is a big no-op, at least until everything
79 * this EDMA driver code to co-exist.
87 device_printf(sc->sc_dev, "%s: called, TODO!\n", __func__); in qcom_ess_edma_hw_reset()
90 * This is where the linux ess-edma driver would reset the in qcom_ess_edma_hw_reset()
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| /freebsd/sys/dev/iavf/ |
| H A D | iavf_txrx_iflib.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
8 * 1. Redistributions of source code must retain the above copyright notice,
34 * @brief Tx/Rx hotpath implementation for the iflib driver
36 * Contains functions used to implement the Tx and Rx hotpaths of the iflib
63 * @brief iflib Tx/Rx operations for head write back
80 * @brief iflib Tx/Rx operations for descriptor write back
97 * iavf_is_tx_desc_done - Check if a Tx descriptor is ready
107 return (((txr->tx_base[idx].cmd_type_offset_bsz >> IAVF_TXD_QW1_DTYPE_SHIFT) in iavf_is_tx_desc_done()
113 * iavf_tso_detect_sparse - detect TSO packets with too many segments
124 * headers require (usually 1). Then we ensure that, for each TSO segment, its
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