xref: /freebsd/sys/contrib/device-tree/Bindings/net/renesas,r9a09g057-gbeth.yaml (revision ae5de77ed78ae54d86cead5604869212e8008e6b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12select:
13  properties:
14    compatible:
15      contains:
16        enum:
17          - renesas,r9a09g056-gbeth
18          - renesas,r9a09g057-gbeth
19          - renesas,rzv2h-gbeth
20  required:
21    - compatible
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - renesas,r9a09g056-gbeth # RZ/V2N
28          - renesas,r9a09g057-gbeth # RZ/V2H(P)
29      - const: renesas,rzv2h-gbeth
30      - const: snps,dwmac-5.20
31
32  reg:
33    maxItems: 1
34
35  clocks:
36    items:
37      - description: CSR clock
38      - description: AXI system clock
39      - description: PTP clock
40      - description: TX clock
41      - description: RX clock
42      - description: TX clock phase-shifted by 180 degrees
43      - description: RX clock phase-shifted by 180 degrees
44
45  clock-names:
46    items:
47      - const: stmmaceth
48      - const: pclk
49      - const: ptp_ref
50      - const: tx
51      - const: rx
52      - const: tx-180
53      - const: rx-180
54
55  interrupts:
56    minItems: 11
57
58  interrupt-names:
59    items:
60      - const: macirq
61      - const: eth_wake_irq
62      - const: eth_lpi
63      - const: rx-queue-0
64      - const: rx-queue-1
65      - const: rx-queue-2
66      - const: rx-queue-3
67      - const: tx-queue-0
68      - const: tx-queue-1
69      - const: tx-queue-2
70      - const: tx-queue-3
71
72  resets:
73    items:
74      - description: AXI power-on system reset
75
76required:
77  - compatible
78  - reg
79  - clocks
80  - clock-names
81  - interrupts
82  - interrupt-names
83  - resets
84
85allOf:
86  - $ref: snps,dwmac.yaml#
87
88unevaluatedProperties: false
89
90examples:
91  - |
92    #include <dt-bindings/clock/renesas-cpg-mssr.h>
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94
95    ethernet@15c30000 {
96        compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
97        reg = <0x15c30000 0x10000>;
98        clocks =  <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
99                  <&ptp_clock>, <&cpg CPG_MOD 0xb8>,
100                  <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,
101                  <&cpg CPG_MOD 0xbb>;
102        clock-names = "stmmaceth", "pclk", "ptp_ref",
103                      "tx", "rx", "tx-180", "rx-180";
104        resets = <&cpg 0xb0>;
105        interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
116        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
117                          "rx-queue-0", "rx-queue-1", "rx-queue-2",
118                          "rx-queue-3", "tx-queue-0", "tx-queue-1",
119                          "tx-queue-2", "tx-queue-3";
120        phy-mode = "rgmii-id";
121        snps,multicast-filter-bins = <256>;
122        snps,perfect-filter-entries = <128>;
123        rx-fifo-depth = <8192>;
124        tx-fifo-depth = <8192>;
125        snps,fixed-burst;
126        snps,force_thresh_dma_mode;
127        snps,axi-config = <&stmmac_axi_setup>;
128        snps,mtl-rx-config = <&mtl_rx_setup>;
129        snps,mtl-tx-config = <&mtl_tx_setup>;
130        snps,txpbl = <32>;
131        snps,rxpbl = <32>;
132        phy-handle = <&phy0>;
133
134        stmmac_axi_setup: stmmac-axi-config {
135            snps,lpi_en;
136            snps,wr_osr_lmt = <0xf>;
137            snps,rd_osr_lmt = <0xf>;
138            snps,blen = <16 8 4 0 0 0 0>;
139        };
140
141        mtl_rx_setup: rx-queues-config {
142            snps,rx-queues-to-use = <4>;
143            snps,rx-sched-sp;
144
145            queue0 {
146                snps,dcb-algorithm;
147                snps,priority = <0x1>;
148                snps,map-to-dma-channel = <0>;
149            };
150
151            queue1 {
152                snps,dcb-algorithm;
153                snps,priority = <0x2>;
154                snps,map-to-dma-channel = <1>;
155            };
156
157            queue2 {
158                snps,dcb-algorithm;
159                snps,priority = <0x4>;
160                snps,map-to-dma-channel = <2>;
161            };
162
163            queue3 {
164                snps,dcb-algorithm;
165                snps,priority = <0x8>;
166                snps,map-to-dma-channel = <3>;
167            };
168        };
169
170        mtl_tx_setup: tx-queues-config {
171            snps,tx-queues-to-use = <4>;
172
173            queue0 {
174                snps,dcb-algorithm;
175                snps,priority = <0x1>;
176            };
177
178            queue1 {
179                snps,dcb-algorithm;
180                snps,priority = <0x2>;
181            };
182
183            queue2 {
184                snps,dcb-algorithm;
185                snps,priority = <0x4>;
186            };
187
188            queue3 {
189                snps,dcb-algorithm;
190                snps,priority = <0x1>;
191            };
192        };
193
194        mdio {
195            #address-cells = <1>;
196            #size-cells = <0>;
197            compatible = "snps,dwmac-mdio";
198
199            phy0: ethernet-phy@0 {
200                reg = <0>;
201            };
202        };
203    };
204