Lines Matching +full:rx +full:- +full:queue +full:- +full:1
10 * 1. Redistributions of source code must retain the above copyright
45 #define MVNETA_RX_QNUM_MAX 1
46 /* XXX: Currently multi-queue can be used on the Tx side only */
50 #define MVNETA_TX_QNUM_MAX 1
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
60 #define MVNETA_QUEUE(n) (1 << (n))
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
99 /* Rx DMA Hardware Parser Registers */
117 /* Rx DMA Miscellaneous Registers */
118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
121 #define MVNETA_RQC 0x2680 /* Receive Queue Command */
123 /* Rx DMA Networking Controller Miscellaneous Registers */
124 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
125 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
129 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
132 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
137 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */
149 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
157 /* Tx DMA Queue Arbiter Registers (Version 1) */
158 #define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */
159 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
161 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
163 /* Transmit Queue Token-Bucket Counter */
165 /* Transmit Queue Token-Bucket Configuration */
168 /* Tx DMA Queue Arbiter Registers (Version 3) */
169 #define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */
170 #define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */
174 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
176 /* Transmit Queue Refill */
178 /* Transmit Queue Max Token-Bucket Size */
180 /* Transmit Queue Token-Bucket Counter */
182 /* Transmit Queue Arbiter Cfg */
184 /* Transmit Queue IPG(valid q=2..3) */
205 #define MVNETA_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */
207 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */
208 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
212 #define MVNETA_PMACC1 0x2c04 /* Port MAC Control 1 */
224 #define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */
239 /* Port Rx Interrupt Threshold */
258 #define MVNETA_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Error Counter 1 */
269 /* MAC MIB Counters 0x3000 - 0x307c */
274 /* Rx */
330 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000)
333 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1)
334 #define MVNETA_BARE_EN(win) ((1 << (win)) & MVNETA_BARE_EN_MASK)
354 #define MVNETA_SMI_OPCODE_READ (1 << 26)
355 #define MVNETA_SMI_READVALID (1 << 27)
356 #define MVNETA_SMI_BUSY (1 << 28)
365 #define MVNETA_EUIC_ETHERINTSUM (1 << 0)
366 #define MVNETA_EUIC_PARITY (1 << 1)
367 #define MVNETA_EUIC_ADDRVIOL (1 << 2)
368 #define MVNETA_EUIC_ADDRVNOMATCH (1 << 3)
369 #define MVNETA_EUIC_SMIDONE (1 << 4)
370 #define MVNETA_EUIC_COUNTWA (1 << 5)
371 #define MVNETA_EUIC_INTADDRERR (1 << 7)
372 #define MVNETA_EUIC_PORT0DPERR (1 << 9)
373 #define MVNETA_EUIC_TOPDPERR (1 << 12)
381 #define MVNETA_EUC_POLLING (1 << 1)
382 #define MVNETA_EUC_PORTRESET (1 << 24)
383 #define MVNETA_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25)
389 #define MVNETA_SDC_RXBSZ(x) ((x) << 1)
392 #define MVNETA_SDC_RXBSZ_2_64BITWORDS MVNETA_SDC_RXBSZ(1)
396 #define MVNETA_SDC_BLMR (1 << 4)
397 #define MVNETA_SDC_BLMT (1 << 5)
398 #define MVNETA_SDC_SWAPMODE (1 << 6)
402 #define MVNETA_SDC_TXBSZ_2_64BITWORDS MVNETA_SDC_TXBSZ(1)
420 * Rx DMA Hardware Parser Registers
423 #define MVNETA_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */
424 #define MVNETA_ETP_ETHERTYPEPRIFRSTEN (1 << 1)
425 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
427 #define MVNETA_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */
431 #define MVNETA_DF_PASS (1 << 0)
432 #define MVNETA_DF_QUEUE(q) ((q) << 1)
433 #define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1)
434 #define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1)
437 * Rx DMA Miscellaneous Registers
439 /* Port Rx Minimal Frame Size (MVNETA_PMFS) */
440 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
442 /* Receive Queue Command (MVNETA_RQC) */
444 #define MVNETA_RQC_ENQ(q) (1 << (0 + (q)))
447 #define MVNETA_RQC_DISQ(q) (1 << (8 + (q)))
451 * Rx DMA Networking Controller Miscellaneous Registers
453 /* Port RX queues Configuration (MVNETA_PRXC) */
456 /* Port RX queues Snoop (MVNETA_PRXSNP) */
460 /* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */
464 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */
470 /* Port RX queues Status (MVNETA_PRXS) */
478 /* Port RX queues Status Update (MVNETA_PRXSU) */
482 /* Port RX Initialization (MVNETA_PRXINIT) */
483 #define MVNETA_PRXINIT_RXDMAINIT (1 << 0)
488 /* Transmit Queue Command (MVNETA_TQC) */
490 #define MVNETA_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */
493 #define MVNETA_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */
499 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */
500 /* Descriptors Queue Size */
527 #define MVNETA_PTXINIT_TXDMAINIT (1 << 0)
530 * Tx DMA Queue Arbiter Registers (Version 1 )
532 /* Transmit Queue Fixed Priority Configuration */
533 #define MVNETA_TQFPC_EN(q) (1 << (q))
539 #define MVNETA_PXC_UPM (1 << 0) /* Uni Promisc mode */
540 #define MVNETA_PXC_RXQ(q) ((q) << 1)
544 #define MVNETA_PXC_RB (1 << 7) /* Rej mode of MAC */
545 #define MVNETA_PXC_RBIP (1 << 8)
546 #define MVNETA_PXC_RBARP (1 << 9)
547 #define MVNETA_PXC_AMNOTXES (1 << 12)
548 #define MVNETA_PXC_RBARPF (1 << 13)
549 #define MVNETA_PXC_TCPCAPEN (1 << 14)
550 #define MVNETA_PXC_UDPCAPEN (1 << 15)
557 #define MVNETA_PXC_RXCS (1 << 25)
560 #define MVNETA_PXCX_SPAN (1 << 1)
561 #define MVNETA_PXCX_TXCRCDIS (1 << 3)
564 #define MVNETA_MH_MHEN (1 << 0)
565 #define MVNETA_MH_DAPREFIX (0x3 << 1)
579 #define MVNETA_PSOMSCD_ENABLE (1UL<<31)
591 #define MVNETA_PSC0_DTE_ADV (1 << 14)
592 #define MVNETA_PSC0_IGN_RXERR (1 << 28)
593 #define MVNETA_PSC0_IGN_COLLISION (1 << 29)
594 #define MVNETA_PSC0_IGN_CARRIER (1 << 30)
597 #define MVNETA_PS0_TXINPROG (1 << 0)
598 #define MVNETA_PS0_TXFIFOEMP (1 << 8)
599 #define MVNETA_PS0_RXFIFOEMPTY (1 << 16)
604 #define MVNETA_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6)
605 #define MVNETA_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2)
608 * Gigabit Ethernet Auto-Negotiation Configuration Registers
610 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */
611 #define MVNETA_PANC_FORCELINKFAIL (1 << 0)
612 #define MVNETA_PANC_FORCELINKPASS (1 << 1)
613 #define MVNETA_PANC_INBANDANEN (1 << 2)
614 #define MVNETA_PANC_INBANDANBYPASSEN (1 << 3)
615 #define MVNETA_PANC_INBANDRESTARTAN (1 << 4)
616 #define MVNETA_PANC_SETMIISPEED (1 << 5)
617 #define MVNETA_PANC_SETGMIISPEED (1 << 6)
618 #define MVNETA_PANC_ANSPEEDEN (1 << 7)
619 #define MVNETA_PANC_SETFCEN (1 << 8)
620 #define MVNETA_PANC_PAUSEADV (1 << 9)
621 #define MVNETA_PANC_ANFCEN (1 << 11)
622 #define MVNETA_PANC_SETFULLDX (1 << 12)
623 #define MVNETA_PANC_ANDUPLEXEN (1 << 13)
624 #define MVNETA_PANC_MUSTSET (1 << 15)
630 #define MVNETA_PMACC0_PORTEN (1 << 0)
631 #define MVNETA_PMACC0_PORTTYPE (1 << 1)
632 #define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) << 2) & 0x7ffc)
634 #define MVNETA_PMACC0_MUSTSET (1 << 15)
636 /* Port MAC Control 1 (MVNETA_PMACC1) */
637 #define MVNETA_PMACC1_PCSLB (1 << 6)
640 #define MVNETA_PMACC2_INBANDANMODE (1 << 0)
641 #define MVNETA_PMACC2_PCSEN (1 << 3)
642 #define MVNETA_PMACC2_PCSEN (1 << 3)
643 #define MVNETA_PMACC2_RGMIIEN (1 << 4)
644 #define MVNETA_PMACC2_PADDINGDIS (1 << 5)
645 #define MVNETA_PMACC2_PORTMACRESET (1 << 6)
646 #define MVNETA_PMACC2_PRBSCHECKEN (1 << 10)
647 #define MVNETA_PMACC2_PRBSGENEN (1 << 11)
650 #define MVNETA_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */
662 #define MVNETA_PI_INTSUM (1 << 0)
663 #define MVNETA_PI_LSC (1 << 1) /* LinkStatus Change */
664 #define MVNETA_PI_ACOP (1 << 2) /* AnCompleted OnPort */
665 #define MVNETA_PI_AOOR (1 << 5) /* AddressOut Of Range */
666 #define MVNETA_PI_SSC (1 << 6) /* SyncStatus Change */
667 #define MVNETA_PI_PRBSEOP (1 << 7) /* QSGMII PRBS error */
668 #define MVNETA_PI_MIBCWA (1 << 15) /* MIB counter wrap around */
669 #define MVNETA_PI_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */
670 #define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
671 #define MVNETA_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
672 #define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
673 #define MVNETA_PI_MIBCCD (1 << 14) /* MIB counters copy done */
682 /* LPI Control 1 (MVNETA_LPIC1) */
683 #define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */
684 #define MVNETA_LPIC1_LPIRF (1 << 1) /* LPI request force */
685 #define MVNETA_LPIC1_LPIMM (1 << 2) /* LPI manual mode */
692 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
693 #define MVNETA_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */
694 #define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
695 #define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
696 #define MVNETA_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */
702 #define MVNETA_PPRBSS_PRBSCHECKLOCKED (1 << 0)
703 #define MVNETA_PPRBSS_PRBSCHECKRDY (1 << 1)
709 #define MVNETA_PSR_LINKUP (1 << 0)
710 #define MVNETA_PSR_GMIISPEED (1 << 1)
711 #define MVNETA_PSR_MIISPEED (1 << 2)
712 #define MVNETA_PSR_FULLDX (1 << 3)
713 #define MVNETA_PSR_RXFCEN (1 << 4)
714 #define MVNETA_PSR_TXFCEN (1 << 5)
715 #define MVNETA_PSR_PRP (1 << 6) /* Port Rx Pause */
716 #define MVNETA_PSR_PTP (1 << 7) /* Port Tx Pause */
717 #define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/
718 #define MVNETA_PSR_SYNCFAIL10MS (1 << 10)
719 #define MVNETA_PSR_ANDONE (1 << 11)
720 #define MVNETA_PSR_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */
721 #define MVNETA_PSR_SYNCOK (1 << 14)
726 /* Port CPU to Queue */
728 #define MVNETA_PCP2Q_TXQEN(q) (1 << ((q) + 8))
730 #define MVNETA_PCP2Q_RXQEN(q) (1 << ((q) + 0))
737 #define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0))
740 /* Tx Buffer Threshold Cross Queue*/
741 #define MVNETA_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8))
744 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */
745 #define MVNETA_PRXTXTI_RDTAQ(q) (1 << ((q) + 16))
748 /* Rx Descriptor Threshold Alert Queue*/
749 #define MVNETA_PRXTXTI_PRXTXICSUMMARY (1 << 29) /* PRXTXI summary */
750 #define MVNETA_PRXTXTI_PTXERRORSUMMARY (1 << 30) /* PTEXERROR summary */
751 #define MVNETA_PRXTXTI_PMISCICSUMMARY (1UL << 31) /* PMISCIC summary */
754 #define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0))
757 #define MVNETA_PRXTXI_RPQ(q) (1 << ((q) + 8))
760 #define MVNETA_PRXTXI_RREQ(q) (1 << ((q) + 16))
763 #define MVNETA_PRXTXI_PRXTXTHICSUMMARY (1 << 29)
764 #define MVNETA_PRXTXI_PTXERRORSUMMARY (1 << 30)
765 #define MVNETA_PRXTXI_PMISCICSUMMARY (1UL << 31)
768 #define MVNETA_PMI_PHYSTATUSCHNG (1 << 0)
769 #define MVNETA_PMI_LINKCHANGE (1 << 1)
770 #define MVNETA_PMI_IAE (1 << 7) /* Internal Address Error */
771 #define MVNETA_PMI_RXOVERRUN (1 << 8)
772 #define MVNETA_PMI_RXCRCERROR (1 << 9)
773 #define MVNETA_PMI_RXLARGEPACKET (1 << 10)
774 #define MVNETA_PMI_TXUNDRN (1 << 11)
775 #define MVNETA_PMI_PRBSERROR (1 << 12)
776 #define MVNETA_PMI_PSCSYNCCHANGE (1 << 13)
777 #define MVNETA_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */
778 #define MVNETA_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */
782 #define MVNETA_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0))
783 #define MVNETA_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8))
801 #define MVNETA_PPLLC_PHY_MODE_SAS (1 << 5)
802 #define MVNETA_PPLLC_PLL_LOCK (1 << 8)
803 #define MVNETA_PPLLC_PU_DFE (1 << 10)
804 #define MVNETA_PPLLC_PU_TX_INTP (1 << 11)
805 #define MVNETA_PPLLC_PU_TX (1 << 12)
806 #define MVNETA_PPLLC_PU_RX (1 << 13)
807 #define MVNETA_PPLLC_PU_PLL (1 << 14)
812 #define MVNETA_DLE_LOCAL_SEL_BITS_20BITS (1 << 10)
814 #define MVNETA_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12)
815 #define MVNETA_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13)
816 #define MVNETA_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14)
817 #define MVNETA_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15)
820 #define MVNETA_RCS_REFCLK_SEL (1 << 10)
857 #define MVNETA_RX_IPV4_FRAGMENT (1UL << 31) /* Fragment Indicator */
858 #define MVNETA_RX_L4_CHECKSUM_OK (1 << 30) /* L4 Checksum */
860 #define MVNETA_RX_U (1 << 28) /* Unknown Destination */
861 #define MVNETA_RX_F (1 << 27) /* First buffer */
862 #define MVNETA_RX_L (1 << 26) /* Last buffer */
863 #define MVNETA_RX_IP_HEADER_OK (1 << 25) /* IP Header is OK */
864 #define MVNETA_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */
865 #define MVNETA_RX_L2_EV2 (1 << 23) /* Ethernet v2 frame */
870 #define MVNETA_RX_BPDU (1 << 20) /* BPDU frame */
871 #define MVNETA_RX_VLAN (1 << 19) /* VLAN tag found */
877 #define MVNETA_RX_ES (1 << 16) /* Error summary */
891 #define MVNETA_TX_CMD_F (1 << 21) /* First buffer */
892 #define MVNETA_TX_CMD_L (1 << 20) /* Last buffer */
893 #define MVNETA_TX_CMD_PADDING (1 << 19) /* Pad short frame */
894 #define MVNETA_TX_CMD_IP4_CHECKSUM (1 << 18) /* Do IPv4 Checksum */
896 #define MVNETA_TX_CMD_L3_IP6 (1 << 17)
898 #define MVNETA_TX_CMD_L4_UDP (1 << 16)
914 #define MVNETA_TX_F_EC_MASK (3 << 1) /* Error code */
915 #define MVNETA_TX_F_EC_LC (0x00 << 1) /* Late Collision */
916 #define MVNETA_TX_F_EC_UR (0x01 << 1) /* Underrun */
917 #define MVNETA_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */
918 #define MVNETA_TX_F_EC_RESERVED (0x11 << 1)
919 #define MVNETA_TX_F_ES (1 << 0) /* Error summary */
921 #define MVNETA_ERROR_SUMMARY (1 << 0)
922 #define MVNETA_BUFFER_OWNED_MASK (1UL << 31)
924 #define MVNETA_BUFFER_OWNED_BY_DMA (1UL << 31)