Lines Matching +full:rx +full:- +full:queue +full:- +full:1
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
10 1. Redistributions of source code must retain the above copyright notice,
73 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
74 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
75 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
198 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
205 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
206 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
207 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
208 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
209 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
210 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
211 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
212 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
257 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
258 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
260 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
267 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
274 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
302 #define E1000_PCS_LCTL_FLV_LINK_UP 1
315 #define E1000_PCS_LSTS_LINK_OK 1
323 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
324 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
327 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
353 #define HALF_DUPLEX 1
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
424 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
474 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */
544 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
546 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
547 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
548 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
549 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
551 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
553 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
564 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
565 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
566 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
567 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
585 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
586 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
587 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
588 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
589 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
590 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
591 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
592 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
618 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
621 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
622 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
623 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
624 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
630 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
631 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
632 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
633 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
640 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
641 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
642 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
643 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
644 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
645 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
646 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
647 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
653 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
654 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
657 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
658 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
659 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
660 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
661 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
662 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
663 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
664 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
678 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
679 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
708 #define E1000_ERR_NVM 1
727 /* Loop limit on how long we wait for auto-negotiation to complete */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
768 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
769 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
775 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
808 #define E1000_ETQF_1588 (1 << 30)
813 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
822 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
831 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
832 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
844 #define E1000_MEDIA_PORT_COPPER 1
862 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
865 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
869 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
878 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
879 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
881 #define E1000_PCS_STATUS_ADDR_I354 1
925 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
931 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
932 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
940 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
976 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
986 /* 1000BASE-T Control Register */
990 /* 1=Repeater/switch device port 0=DTE device */
992 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
994 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
1002 /* 1000BASE-T Status Register */
1009 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1018 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1039 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1044 /* NVM Addressing bits based on type 0=small, 1=large */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1075 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1077 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1302 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1310 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1313 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1314 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1315 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1323 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1324 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1325 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1366 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1379 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1460 /* DMA Coalescing Rx Threshold */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1475 /* Rx Traffic Rate Threshold */
1477 /* Rx packet rate in current window */
1480 /* DMA Coal Rx Traffic Current Count */
1483 /* Flow ctrl Rx Threshold High val */
1489 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1490 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */