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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
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H A Dfsl,qoriq-clock-legacy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
24 - fsl,qoriq-core-mux-1.0
25 - fsl,qoriq-core-mux-2.0
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H A Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
17 either an oscillator or a pll output.
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H A Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda highbank platform Clock Controller
13 "hb-sregs" node.
16 - Andre Przywara <andre.przywara@arm.com>
19 "#clock-cells":
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
26 - calxeda,hb-a9bus-clock
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/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock driver for TI Davinci SoCs
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
22 #include <linux/platform_data/clk-davinci-pll.h>
29 #include "pll.h"
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
86 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
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H A Dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/clk-provider.h>
17 #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
18 #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */
21 #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */
28 /** davinci_pll_clk_info - controller-specific PLL info
29 * @name: The name of the PLL
30 * @unlock_reg: Option CFGCHIP register for unlocking PLL
55 /** davinci_pll_sysclk_info - SYSCLKn-specific info
79 /** davinci_pll_obsclk_info - OBSCLK-specific info
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/linux/drivers/clk/samsung/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
15 #include "clk-cpu.h"
18 * struct samsung_clk_provider - information about clock provider
21 * @lock: maintains exclusion between callbacks for a given clock-provider
33 * struct samsung_clock_alias - information about mux clock
34 * @id: platform specific id of the clock
54 * struct samsung_fixed_rate_clock - information about fixed-rate clock
55 * @id: platform specific id of the clock
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/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
21 #include <sound/soc-acpi.h>
23 #include "../atom/sst-atom-controls.h"
24 #include "../common/soc-intel-quirks.h"
27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
29 #define CHT_CODEC_DAI "rt5670-aif1"
53 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
54 struct snd_soc_card *card = dapm->card; in platform_clock_control()
61 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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H A Dsof_da7219.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/soc-acpi.h>
21 /* Driver-specific board quirks: from bit 0 to 7 */
27 #define DIALOG_CODEC_DAI "da7219-hifi"
32 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
33 struct snd_soc_card *card = dapm->card; in platform_clock_control()
38 if (ctx->da7219.pll_bypass) in platform_clock_control()
41 /* PLL SRM mode */ in platform_clock_control()
44 dev_err(card->dev, "Codec dai not found; Unable to set/unset codec pll\n"); in platform_clock_control()
45 return -EIO; in platform_clock_control()
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H A Dbdw-rt5650.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <sound/soc-acpi.h>
91 /* The ADSP will convert the FE rate to 48k, max 4-channels */ in broadwell_ssp0_fixup()
92 rate->min = rate->max = 48000; in broadwell_ssp0_fixup()
93 chan->min = 2; in broadwell_ssp0_fixup()
94 chan->max = 4; in broadwell_ssp0_fixup()
110 /* Workaround: set codec PLL to 19.2MHz that PLL source is in bdw_rt5650_hw_params()
116 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); in bdw_rt5650_hw_params()
127 dev_err(rtd->dev, "can't set codec sysclk configuration\n"); in bdw_rt5650_hw_params()
150 struct snd_pcm_runtime *runtime = substream->runtime; in bdw_rt5650_fe_startup()
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H A Dbytcr_wm5102.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_wm5102.c - ASoc Machine driver for Intel Baytrail platforms with a
8 * Copyright (C) 2014-2020 Intel Corp
27 #include <sound/soc-acpi.h>
29 #include "../atom/sst-atom-controls.h"
51 /* Note these values are pre-shifted for easy use of setting quirks */
59 static int quirk_override = -1;
61 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
102 struct snd_soc_card *card = w->dapm->card; in byt_wm5102_spkvdd_power_event()
105 gpiod_set_value_cansleep(priv->spkvdd_en_gpio, in byt_wm5102_spkvdd_power_event()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
48 * enum intel_dpll_id - possible DPLL ids
54 * @DPLL_ID_PRIVATE: non-shared dpll in use
56 DPLL_ID_PRIVATE = -1,
125 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
129 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
130 * TGL TC PLL 1 port 1 (TC1)
134 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
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/linux/sound/soc/fsl/
H A Dfsl_utils.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
18 * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
42 return -EINVAL; in fsl_asoc_get_dma_channel()
44 if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) { in fsl_asoc_get_dma_channel()
46 return -EINVAL; in fsl_asoc_get_dma_channel()
51 * the dev_name() of the device to match the platform (DMA) device with in fsl_asoc_get_dma_channel()
55 * dai->platform name should already point to an allocated buffer. in fsl_asoc_get_dma_channel()
62 snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn", in fsl_asoc_get_dma_channel()
65 iprop = of_get_property(dma_channel_np, "cell-index", NULL); in fsl_asoc_get_dma_channel()
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/linux/Documentation/driver-api/
H A Dsm501.rst15 ----
23 chips via the platform device and driver system.
26 be specified by the platform data) and then exports the selected
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
31 need to create a new bus-type and the associated code to go with it.
35 ---------
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
61 The platform device driver uses a set of platform data to pass
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/linux/sound/soc/intel/avs/boards/
H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation
15 #include <sound/soc-acpi.h>
16 #include <sound/soc-dapm.h>
17 #include <uapi/linux/input-event-codes.h>
21 #define DA7219_DAI_NAME "da7219-hifi"
32 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
33 struct snd_soc_card *card = dapm->card; in platform_clock_control()
39 dev_err(card->dev, "Codec dai not found. Unable to set/unset codec pll\n"); in platform_clock_control()
40 return -EIO; in platform_clock_control()
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/linux/drivers/accel/ivpu/
H A Divpu_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 - 2024 Intel Corporation
13 static char *platform_to_str(u32 platform) in platform_to_str() argument
15 switch (platform) { in platform_to_str()
23 return "Invalid platform"; in platform_to_str()
48 vdev->platform = IVPU_PLATFORM_SIMICS; in platform_init()
50 vdev->platform = IVPU_PLATFORM_SILICON; in platform_init()
52 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in platform_init()
53 platform_to_str(vdev->platform), vdev->platform); in platform_init()
58 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); in wa_init()
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/linux/drivers/clk/
H A Dclk-qoriq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <linux/clk-provider.h>
33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
48 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
52 int pll; /* CGx_PLLn */ member
68 * cmux freq must be >= platform pll.
69 * If not set, cmux freq must be >= platform pll/2
82 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
83 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 by platform/architecture code. This method is deprecated. Modern
46 bool "PLL Driver for HSDK platform"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
202 Given a target output frequency, the driver will set the PLL and
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/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Dynamic Platform and Thermal Framework Sysfs Interface
12 ------------
14 Intel(R) Dynamic Platform and Thermal Framework (DPTF) is a platform
21 Since it is a platform level framework, this has several components.
26 "Linux Thermal Daemon" to read platform specific thermal and power
31 ----------------------------
33 :file:`/sys/bus/platform/devices/<N>/uuids`, where <N>
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
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/linux/arch/arm/boot/dts/vt8500/
H A Dwm8850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
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H A Dwm8750.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <0>;
15 #size-cells = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
44 interrupt-parent = <&intc0>;
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/linux/drivers/clk/meson/
H A Da1-pll.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "a1-pll.h"
14 #include "clk-regmap.h"
15 #include "meson-clkc-utils.h"
17 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
168 * and is required by the platform to operate correctly.
172 * b) CCF has a clock hand-off mechanism to make the sure the
206 * and is required by the platform to operate correctly.
239 * and is required by the platform to operate correctly.
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/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
34 * enum si5351_clkout_src - Si5351 clock output clock source
51 * enum si5351_drive_strength - Si5351 clock output drive strength
67 * enum si5351_disable_state - Si5351 clock output disable state
84 * struct si5351_clkout_config - Si5351 clock output configuration
88 * @pll_master: if true, clkout can also change pll rate
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/linux/include/media/i2c/
H A Dadv7343.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
16 * struct adv7343_power_mode - power mode configuration.
18 * level. All DACs and the internal PLL circuit are disabled.
20 * @pll_control: PLL and oversampling control. This control allows internal
21 * PLL 1 circuit to be powered down and the oversampling to be
28 * [1] http://www.analog.com/static/imported-files/data_sheets/ADV7342_7343.pdf
37 * struct adv7343_sd_config - SD Only Output Configuration.
46 * struct adv7343_platform_data - Platform data values and access functions.
/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
52 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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