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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
[all …]
H A Dhisilicon,phy-hi3670-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin970 PCIe PHY
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
13 Bindings for PCIe PHY on HiSilicon Kirin 970.
17 const: hisilicon,hi970-pcie-phy
19 "#phy-cells":
20 const: 0
[all …]
H A Dbrcm,cygnus-pcie-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Cygnus PCIe PHY
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
15 pattern: "^pcie[-|_]phy(@.*)?$"
19 - const: brcm,cygnus-pcie-phy
24 Base address and length of the PCIe PHY block
[all …]
H A Dairoha,en7581-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 PCI-Express PHY
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
17 const: airoha,en7581-pcie-phy
21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
[all …]
H A Dlantiq,vrx200-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
[all …]
H A Dqcom,ipq8074-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dsocionext,uniphier-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
[all …]
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
14 const: 0
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
[all …]
H A Dbrcm,sr-pcie-phy.txt1 Broadcom Stingray PCIe PHY
4 - compatible: must be "brcm,sr-pcie-phy"
5 - reg: base address and length of the PCIe SS register space
6 - brcm,sr-cdru: phandle to the CDRU syscon node
7 - brcm,sr-mhb: phandle to the MHB syscon node
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
17 compatible = "brcm,sr-mhb", "syscon";
18 reg = <0 0x60401000 0 0x38c>;
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dsamsung,exynos-pcie-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe PHY
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 "#phy-cells":
15 const: 0
18 const: samsung,exynos5433-pcie-phy
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
13 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-armada8k.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
37 #define PCIE_VENDOR_REGS_OFFSET 0x8000
39 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
42 #define PCIE_DEVICE_TYPE_MASK 0xF
43 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
[all …]
H A Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
20 #include <linux/phy/phy.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
31 /* PCIe ELBI registers */
32 #define SOC_PCIECTRL_CTRL0_ADDR 0x000
33 #define SOC_PCIECTRL_CTRL1_ADDR 0x004
34 #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
37 #define PCIE_APP_LTSSM_ENABLE 0x01c
[all …]
H A Dpcie-intel-gw.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
14 #include <linux/phy/phy.h>
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
27 #define PCIE_APP_CCR 0x10
28 #define PCIE_APP_CCR_LTSSM_ENABLE BIT(0)
30 #define PCIE_APP_MSG_CR 0x30
31 #define PCIE_APP_MSG_XMT_PM_TURNOFF BIT(0)
[all …]
H A Dpcie-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
19 #include <linux/phy/phy.h>
23 #include "pcie-designware.h"
25 #define PCL_PINCTRL0 0x002c
31 #define PCL_PERST_OUT_REGVAL BIT(0)
33 #define PCL_PIPEMON 0x0044
36 #define PCL_MODE 0x8000
38 #define PCL_MODE_REGVAL BIT(0)
40 #define PCL_APP_READY_CTRL 0x8008
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-starfive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for StarFive JH7110 Soc.
20 #include <linux/phy/phy.h>
27 #include "pcie-plda.h"
32 #define STG_SYSCON_PCIE0_BASE 0x48
33 #define STG_SYSCON_PCIE1_BASE 0x1f8
35 #define STG_SYSCON_AR_OFFSET 0x78
38 #define STG_SYSCON_AW_OFFSET 0x7c
39 #define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0)
43 #define STG_SYSCON_RP_NEP_OFFSET 0xe8
[all …]
/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
11 #include <linux/clk-provider.h>
23 #include <linux/phy/phy.h>
31 #define PCIE_SETTING_REG 0x80
32 #define PCIE_PCI_IDS_1 0x9c
34 #define PCIE_RC_MODE BIT(0)
36 #define PCIE_EQ_PRESET_01_REG 0x100
37 #define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)
42 #define PCIE_CFGNUM_REG 0x140
[all …]
H A Dpcie-mt7621.c1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
28 #include <linux/phy/phy.h>
35 /* MediaTek-specific configuration registers */
36 #define PCIE_FTS_NUM 0x70c
38 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
40 /* Host-PCI bridge registers */
41 #define RALINK_PCI_PCICFG_ADDR 0x0000
42 #define RALINK_PCI_PCIMSK_ADDR 0x000c
[all …]
H A Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
22 #include <linux/phy/phy.h>
29 #define BRCFG_PCIE_RX0 0x00000000
30 #define BRCFG_PCIE_RX1 0x00000004
31 #define BRCFG_INTERRUPT 0x00000010
32 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
[all …]
H A Dpcie-iproc-platform.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/phy/phy.h>
19 #include "pcie-iproc.h"
23 .compatible = "brcm,iproc-pcie",
26 .compatible = "brcm,iproc-pcie-paxb-v2",
29 .compatible = "brcm,iproc-pcie-paxc",
32 .compatible = "brcm,iproc-pcie-paxc-v2",
41 struct device *dev = &pdev->dev; in iproc_pltfm_pcie_probe()
42 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
43 struct device_node *np = dev->of_node; in iproc_pltfm_pcie_probe()
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
20 #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
21 #define PCIE_PIPEMUX_SELECT_STRAP 0xf
23 #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
25 #define PCIE_PIPEMUX_MASK 0xf
27 #define MHB_MEM_PW_PAXC_OFFSET 0x1c0
28 #define MHB_PWR_ARR_POWERON 0x8
[all …]
H A Dphy-bcm-cygnus-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
11 #define PCIE_CFG_OFFSET 0x00
16 CYGNUS_PHY_PCIE0 = 0,
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
[all …]

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