1*5dfb2d24SMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*5dfb2d24SMauro Carvalho Chehab%YAML 1.2 3*5dfb2d24SMauro Carvalho Chehab--- 4*5dfb2d24SMauro Carvalho Chehab$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# 5*5dfb2d24SMauro Carvalho Chehab$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5dfb2d24SMauro Carvalho Chehab 7*5dfb2d24SMauro Carvalho Chehabtitle: HiSilicon Kirin970 PCIe PHY 8*5dfb2d24SMauro Carvalho Chehab 9*5dfb2d24SMauro Carvalho Chehabmaintainers: 10*5dfb2d24SMauro Carvalho Chehab - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 11*5dfb2d24SMauro Carvalho Chehab 12*5dfb2d24SMauro Carvalho Chehabdescription: |+ 13*5dfb2d24SMauro Carvalho Chehab Bindings for PCIe PHY on HiSilicon Kirin 970. 14*5dfb2d24SMauro Carvalho Chehab 15*5dfb2d24SMauro Carvalho Chehabproperties: 16*5dfb2d24SMauro Carvalho Chehab compatible: 17*5dfb2d24SMauro Carvalho Chehab const: hisilicon,hi970-pcie-phy 18*5dfb2d24SMauro Carvalho Chehab 19*5dfb2d24SMauro Carvalho Chehab "#phy-cells": 20*5dfb2d24SMauro Carvalho Chehab const: 0 21*5dfb2d24SMauro Carvalho Chehab 22*5dfb2d24SMauro Carvalho Chehab reg: 23*5dfb2d24SMauro Carvalho Chehab maxItems: 1 24*5dfb2d24SMauro Carvalho Chehab description: PHY Control registers 25*5dfb2d24SMauro Carvalho Chehab 26*5dfb2d24SMauro Carvalho Chehab phy-supply: 27*5dfb2d24SMauro Carvalho Chehab description: The PCIe PHY power supply 28*5dfb2d24SMauro Carvalho Chehab 29*5dfb2d24SMauro Carvalho Chehab clocks: 30*5dfb2d24SMauro Carvalho Chehab items: 31*5dfb2d24SMauro Carvalho Chehab - description: PCIe PHY clock 32*5dfb2d24SMauro Carvalho Chehab - description: PCIe AUX clock 33*5dfb2d24SMauro Carvalho Chehab - description: PCIe APB PHY clock 34*5dfb2d24SMauro Carvalho Chehab - description: PCIe APB SYS clock 35*5dfb2d24SMauro Carvalho Chehab - description: PCIe ACLK clock 36*5dfb2d24SMauro Carvalho Chehab 37*5dfb2d24SMauro Carvalho Chehab clock-names: 38*5dfb2d24SMauro Carvalho Chehab items: 39*5dfb2d24SMauro Carvalho Chehab - const: phy_ref 40*5dfb2d24SMauro Carvalho Chehab - const: aux 41*5dfb2d24SMauro Carvalho Chehab - const: apb_phy 42*5dfb2d24SMauro Carvalho Chehab - const: apb_sys 43*5dfb2d24SMauro Carvalho Chehab - const: aclk 44*5dfb2d24SMauro Carvalho Chehab 45*5dfb2d24SMauro Carvalho Chehab hisilicon,eye-diagram-param: 46*5dfb2d24SMauro Carvalho Chehab $ref: /schemas/types.yaml#/definitions/uint32-array 47*5dfb2d24SMauro Carvalho Chehab description: Eye diagram for phy. 48*5dfb2d24SMauro Carvalho Chehab 49*5dfb2d24SMauro Carvalho Chehabrequired: 50*5dfb2d24SMauro Carvalho Chehab - "#phy-cells" 51*5dfb2d24SMauro Carvalho Chehab - compatible 52*5dfb2d24SMauro Carvalho Chehab - reg 53*5dfb2d24SMauro Carvalho Chehab - clocks 54*5dfb2d24SMauro Carvalho Chehab - clock-names 55*5dfb2d24SMauro Carvalho Chehab - hisilicon,eye-diagram-param 56*5dfb2d24SMauro Carvalho Chehab - phy-supply 57*5dfb2d24SMauro Carvalho Chehab 58*5dfb2d24SMauro Carvalho ChehabadditionalProperties: false 59*5dfb2d24SMauro Carvalho Chehab 60*5dfb2d24SMauro Carvalho Chehabexamples: 61*5dfb2d24SMauro Carvalho Chehab - | 62*5dfb2d24SMauro Carvalho Chehab #include <dt-bindings/clock/hi3670-clock.h> 63*5dfb2d24SMauro Carvalho Chehab 64*5dfb2d24SMauro Carvalho Chehab soc { 65*5dfb2d24SMauro Carvalho Chehab #address-cells = <2>; 66*5dfb2d24SMauro Carvalho Chehab #size-cells = <2>; 67*5dfb2d24SMauro Carvalho Chehab pcie_phy: pcie-phy@fc000000 { 68*5dfb2d24SMauro Carvalho Chehab compatible = "hisilicon,hi970-pcie-phy"; 69*5dfb2d24SMauro Carvalho Chehab reg = <0x0 0xfc000000 0x0 0x80000>; 70*5dfb2d24SMauro Carvalho Chehab #phy-cells = <0>; 71*5dfb2d24SMauro Carvalho Chehab phy-supply = <&ldo33>; 72*5dfb2d24SMauro Carvalho Chehab clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, 73*5dfb2d24SMauro Carvalho Chehab <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, 74*5dfb2d24SMauro Carvalho Chehab <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, 75*5dfb2d24SMauro Carvalho Chehab <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, 76*5dfb2d24SMauro Carvalho Chehab <&crg_ctrl HI3670_ACLK_GATE_PCIE>; 77*5dfb2d24SMauro Carvalho Chehab clock-names = "phy_ref", "aux", 78*5dfb2d24SMauro Carvalho Chehab "apb_phy", "apb_sys", "aclk"; 79*5dfb2d24SMauro Carvalho Chehab hisilicon,eye-diagram-param = <0xffffffff 0xffffffff 80*5dfb2d24SMauro Carvalho Chehab 0xffffffff 0xffffffff 0xffffffff>; 81*5dfb2d24SMauro Carvalho Chehab }; 82*5dfb2d24SMauro Carvalho Chehab }; 83