Lines Matching +full:pcie +full:- +full:phy +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
20 #include <linux/phy/phy.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
31 /* PCIe ELBI registers */
32 #define SOC_PCIECTRL_CTRL0_ADDR 0x000
33 #define SOC_PCIECTRL_CTRL1_ADDR 0x004
34 #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
37 #define PCIE_APP_LTSSM_ENABLE 0x01c
38 #define PCIE_APB_PHY_STATUS0 0x400
39 #define PCIE_LINKUP_ENABLE (0x8020)
40 #define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
43 #define SCTRL_PCIE_CMOS_OFFSET 0x60
44 #define SCTRL_PCIE_CMOS_BIT 0x10
45 #define SCTRL_PCIE_ISO_OFFSET 0x44
46 #define SCTRL_PCIE_ISO_BIT 0x30
47 #define SCTRL_PCIE_HPCLK_OFFSET 0x190
48 #define SCTRL_PCIE_HPCLK_BIT 0x184000
49 #define SCTRL_PCIE_OE_OFFSET 0x14a
50 #define PCIE_DEBOUNCE_PARAM 0xF0F400
51 #define PCIE_OE_BYPASS (0x3 << 28)
57 * lanes (lane 0 upstream, and the other three lanes, one connected to an
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
75 struct phy *phy; member
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
93 * Kirin 960 PHY. Can't be split into a PHY driver without changing the
99 /* PHY info located in APB */
100 #define PCIE_APB_PHY_CTRL0 0x0
101 #define PCIE_APB_PHY_CTRL1 0x4
102 #define PCIE_APB_PHY_STATUS0 0x400
109 #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
110 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
140 writel(val, hi3660_pcie_phy->base + reg); in kirin_apb_phy_writel()
146 return readl(hi3660_pcie_phy->base + reg); in kirin_apb_phy_readl()
149 static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy) in hi3660_pcie_phy_get_clk() argument
151 struct device *dev = phy->dev; in hi3660_pcie_phy_get_clk()
153 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); in hi3660_pcie_phy_get_clk()
154 if (IS_ERR(phy->phy_ref_clk)) in hi3660_pcie_phy_get_clk()
155 return PTR_ERR(phy->phy_ref_clk); in hi3660_pcie_phy_get_clk()
157 phy->aux_clk = devm_clk_get(dev, "pcie_aux"); in hi3660_pcie_phy_get_clk()
158 if (IS_ERR(phy->aux_clk)) in hi3660_pcie_phy_get_clk()
159 return PTR_ERR(phy->aux_clk); in hi3660_pcie_phy_get_clk()
161 phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); in hi3660_pcie_phy_get_clk()
162 if (IS_ERR(phy->apb_phy_clk)) in hi3660_pcie_phy_get_clk()
163 return PTR_ERR(phy->apb_phy_clk); in hi3660_pcie_phy_get_clk()
165 phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); in hi3660_pcie_phy_get_clk()
166 if (IS_ERR(phy->apb_sys_clk)) in hi3660_pcie_phy_get_clk()
167 return PTR_ERR(phy->apb_sys_clk); in hi3660_pcie_phy_get_clk()
169 phy->aclk = devm_clk_get(dev, "pcie_aclk"); in hi3660_pcie_phy_get_clk()
170 if (IS_ERR(phy->aclk)) in hi3660_pcie_phy_get_clk()
171 return PTR_ERR(phy->aclk); in hi3660_pcie_phy_get_clk()
173 return 0; in hi3660_pcie_phy_get_clk()
176 static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) in hi3660_pcie_phy_get_resource() argument
178 struct device *dev = phy->dev; in hi3660_pcie_phy_get_resource()
184 phy->base = devm_platform_ioremap_resource_byname(pdev, "phy"); in hi3660_pcie_phy_get_resource()
185 if (IS_ERR(phy->base)) in hi3660_pcie_phy_get_resource()
186 return PTR_ERR(phy->base); in hi3660_pcie_phy_get_resource()
188 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); in hi3660_pcie_phy_get_resource()
189 if (IS_ERR(phy->crgctrl)) in hi3660_pcie_phy_get_resource()
190 return PTR_ERR(phy->crgctrl); in hi3660_pcie_phy_get_resource()
192 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); in hi3660_pcie_phy_get_resource()
193 if (IS_ERR(phy->sysctrl)) in hi3660_pcie_phy_get_resource()
194 return PTR_ERR(phy->sysctrl); in hi3660_pcie_phy_get_resource()
196 return 0; in hi3660_pcie_phy_get_resource()
199 static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy) in hi3660_pcie_phy_start() argument
201 struct device *dev = phy->dev; in hi3660_pcie_phy_start()
204 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); in hi3660_pcie_phy_start()
206 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); in hi3660_pcie_phy_start()
208 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0); in hi3660_pcie_phy_start()
210 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0); in hi3660_pcie_phy_start()
213 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); in hi3660_pcie_phy_start()
215 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); in hi3660_pcie_phy_start()
218 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0); in hi3660_pcie_phy_start()
221 return -EINVAL; in hi3660_pcie_phy_start()
224 return 0; in hi3660_pcie_phy_start()
227 static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy) in hi3660_pcie_phy_oe_enable() argument
231 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3660_pcie_phy_oe_enable()
234 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3660_pcie_phy_oe_enable()
237 static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable) in hi3660_pcie_phy_clk_ctrl() argument
239 int ret = 0; in hi3660_pcie_phy_clk_ctrl()
244 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); in hi3660_pcie_phy_clk_ctrl()
248 ret = clk_prepare_enable(phy->phy_ref_clk); in hi3660_pcie_phy_clk_ctrl()
252 ret = clk_prepare_enable(phy->apb_sys_clk); in hi3660_pcie_phy_clk_ctrl()
256 ret = clk_prepare_enable(phy->apb_phy_clk); in hi3660_pcie_phy_clk_ctrl()
260 ret = clk_prepare_enable(phy->aclk); in hi3660_pcie_phy_clk_ctrl()
264 ret = clk_prepare_enable(phy->aux_clk); in hi3660_pcie_phy_clk_ctrl()
268 return 0; in hi3660_pcie_phy_clk_ctrl()
271 clk_disable_unprepare(phy->aux_clk); in hi3660_pcie_phy_clk_ctrl()
273 clk_disable_unprepare(phy->aclk); in hi3660_pcie_phy_clk_ctrl()
275 clk_disable_unprepare(phy->apb_phy_clk); in hi3660_pcie_phy_clk_ctrl()
277 clk_disable_unprepare(phy->apb_sys_clk); in hi3660_pcie_phy_clk_ctrl()
279 clk_disable_unprepare(phy->phy_ref_clk); in hi3660_pcie_phy_clk_ctrl()
284 static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) in hi3660_pcie_phy_power_on() argument
286 struct hi3660_pcie_phy *phy = pcie->phy_priv; in hi3660_pcie_phy_power_on() local
290 regmap_write(phy->sysctrl, in hi3660_pcie_phy_power_on()
294 hi3660_pcie_phy_oe_enable(phy); in hi3660_pcie_phy_power_on()
296 ret = hi3660_pcie_phy_clk_ctrl(phy, true); in hi3660_pcie_phy_power_on()
300 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ in hi3660_pcie_phy_power_on()
301 regmap_write(phy->sysctrl, in hi3660_pcie_phy_power_on()
303 regmap_write(phy->crgctrl, in hi3660_pcie_phy_power_on()
305 regmap_write(phy->sysctrl, in hi3660_pcie_phy_power_on()
308 ret = hi3660_pcie_phy_start(phy); in hi3660_pcie_phy_power_on()
312 return 0; in hi3660_pcie_phy_power_on()
315 hi3660_pcie_phy_clk_ctrl(phy, false); in hi3660_pcie_phy_power_on()
320 struct kirin_pcie *pcie) in hi3660_pcie_phy_init() argument
322 struct device *dev = &pdev->dev; in hi3660_pcie_phy_init()
323 struct hi3660_pcie_phy *phy; in hi3660_pcie_phy_init() local
326 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in hi3660_pcie_phy_init()
327 if (!phy) in hi3660_pcie_phy_init()
328 return -ENOMEM; in hi3660_pcie_phy_init()
330 pcie->phy_priv = phy; in hi3660_pcie_phy_init()
331 phy->dev = dev; in hi3660_pcie_phy_init()
333 ret = hi3660_pcie_phy_get_clk(phy); in hi3660_pcie_phy_init()
337 return hi3660_pcie_phy_get_resource(phy); in hi3660_pcie_phy_init()
340 static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie) in hi3660_pcie_phy_power_off() argument
342 struct hi3660_pcie_phy *phy = pcie->phy_priv; in hi3660_pcie_phy_power_off() local
345 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00); in hi3660_pcie_phy_power_off()
347 hi3660_pcie_phy_clk_ctrl(phy, false); in hi3660_pcie_phy_power_off()
349 return 0; in hi3660_pcie_phy_power_off()
353 * The non-PHY part starts here
363 static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie, in kirin_pcie_get_gpio_enable() argument
366 struct device *dev = &pdev->dev; in kirin_pcie_get_gpio_enable()
371 if (ret < 0) in kirin_pcie_get_gpio_enable()
372 return 0; in kirin_pcie_get_gpio_enable()
376 return -EINVAL; in kirin_pcie_get_gpio_enable()
379 pcie->n_gpio_clkreq = ret; in kirin_pcie_get_gpio_enable()
381 for (i = 0; i < pcie->n_gpio_clkreq; i++) { in kirin_pcie_get_gpio_enable()
382 pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev, in kirin_pcie_get_gpio_enable()
385 if (IS_ERR(pcie->id_clkreq_gpio[i])) in kirin_pcie_get_gpio_enable()
386 return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]), in kirin_pcie_get_gpio_enable()
389 pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL, in kirin_pcie_get_gpio_enable()
391 if (!pcie->clkreq_names[i]) in kirin_pcie_get_gpio_enable()
392 return -ENOMEM; in kirin_pcie_get_gpio_enable()
394 gpiod_set_consumer_name(pcie->id_clkreq_gpio[i], in kirin_pcie_get_gpio_enable()
395 pcie->clkreq_names[i]); in kirin_pcie_get_gpio_enable()
398 return 0; in kirin_pcie_get_gpio_enable()
401 static int kirin_pcie_parse_port(struct kirin_pcie *pcie, in kirin_pcie_parse_port() argument
405 struct device *dev = &pdev->dev; in kirin_pcie_parse_port()
410 i = pcie->num_slots; in kirin_pcie_parse_port()
412 pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev, in kirin_pcie_parse_port()
414 "reset", 0, GPIOD_OUT_LOW, in kirin_pcie_parse_port()
416 if (IS_ERR(pcie->id_reset_gpio[i])) { in kirin_pcie_parse_port()
417 if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT) in kirin_pcie_parse_port()
419 return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]), in kirin_pcie_parse_port()
423 if (pcie->num_slots + 1 >= MAX_PCI_SLOTS) { in kirin_pcie_parse_port()
425 return -EINVAL; in kirin_pcie_parse_port()
427 pcie->num_slots++; in kirin_pcie_parse_port()
430 if (ret < 0) { in kirin_pcie_parse_port()
437 pcie->reset_names[i] = devm_kasprintf(dev, GFP_KERNEL, in kirin_pcie_parse_port()
440 if (!pcie->reset_names[i]) in kirin_pcie_parse_port()
441 return -ENOMEM; in kirin_pcie_parse_port()
443 gpiod_set_consumer_name(pcie->id_reset_gpio[i], in kirin_pcie_parse_port()
444 pcie->reset_names[i]); in kirin_pcie_parse_port()
448 return 0; in kirin_pcie_parse_port()
454 struct device *dev = &pdev->dev; in kirin_pcie_get_resource()
455 struct device_node *child, *node = dev->of_node; in kirin_pcie_get_resource()
463 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, in kirin_pcie_get_resource()
465 if (IS_ERR(kirin_pcie->apb)) in kirin_pcie_get_resource()
466 return PTR_ERR(kirin_pcie->apb); in kirin_pcie_get_resource()
468 /* pcie internal PERST# gpio */ in kirin_pcie_get_resource()
469 kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); in kirin_pcie_get_resource()
470 if (IS_ERR(kirin_pcie->id_dwc_perst_gpio)) in kirin_pcie_get_resource()
471 return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio), in kirin_pcie_get_resource()
473 gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge"); in kirin_pcie_get_resource()
486 return 0; in kirin_pcie_get_resource()
498 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val); in kirin_pcie_sideband_dbi_w_mode()
504 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val); in kirin_pcie_sideband_dbi_w_mode()
512 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val); in kirin_pcie_sideband_dbi_r_mode()
518 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val); in kirin_pcie_sideband_dbi_r_mode()
524 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); in kirin_pcie_rd_own_conf()
536 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); in kirin_pcie_wr_own_conf()
547 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); in kirin_pcie_add_bus()
551 if (!kirin_pcie->num_slots) in kirin_pcie_add_bus()
552 return 0; in kirin_pcie_add_bus()
555 for (i = 0; i < kirin_pcie->num_slots; i++) { in kirin_pcie_add_bus()
556 ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1); in kirin_pcie_add_bus()
558 dev_err(pci->dev, "PERST# %s error: %d\n", in kirin_pcie_add_bus()
559 kirin_pcie->reset_names[i], ret); in kirin_pcie_add_bus()
564 return 0; in kirin_pcie_add_bus()
601 regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); in kirin_pcie_link_up()
605 return 0; in kirin_pcie_link_up()
613 regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE, in kirin_pcie_start_link()
616 return 0; in kirin_pcie_start_link()
621 pp->bridge->ops = &kirin_pci_ops; in kirin_pcie_host_init()
623 return 0; in kirin_pcie_host_init()
641 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) in kirin_pcie_power_off()
644 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) in kirin_pcie_power_off()
645 gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1); in kirin_pcie_power_off()
647 phy_power_off(kirin_pcie->phy); in kirin_pcie_power_off()
648 phy_exit(kirin_pcie->phy); in kirin_pcie_power_off()
650 return 0; in kirin_pcie_power_off()
656 struct device *dev = &pdev->dev; in kirin_pcie_power_on()
659 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { in kirin_pcie_power_on()
668 kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); in kirin_pcie_power_on()
669 if (IS_ERR(kirin_pcie->phy)) in kirin_pcie_power_on()
670 return PTR_ERR(kirin_pcie->phy); in kirin_pcie_power_on()
672 ret = phy_init(kirin_pcie->phy); in kirin_pcie_power_on()
676 ret = phy_power_on(kirin_pcie->phy); in kirin_pcie_power_on()
684 ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1); in kirin_pcie_power_on()
690 return 0; in kirin_pcie_power_on()
701 dw_pcie_host_deinit(&kirin_pcie->pci->pp); in kirin_pcie_remove()
719 { .compatible = "hisilicon,kirin960-pcie", .data = &kirin_960_data },
720 { .compatible = "hisilicon,kirin970-pcie", .data = &kirin_970_data },
726 struct device *dev = &pdev->dev; in kirin_pcie_probe()
732 if (!dev->of_node) { in kirin_pcie_probe()
734 return -EINVAL; in kirin_pcie_probe()
740 return -EINVAL; in kirin_pcie_probe()
745 return -ENOMEM; in kirin_pcie_probe()
749 return -ENOMEM; in kirin_pcie_probe()
751 pci->dev = dev; in kirin_pcie_probe()
752 pci->ops = &kirin_dw_pcie_ops; in kirin_pcie_probe()
753 pci->pp.ops = &kirin_pcie_host_ops; in kirin_pcie_probe()
754 kirin_pcie->pci = pci; in kirin_pcie_probe()
755 kirin_pcie->type = data->phy_type; in kirin_pcie_probe()
767 return dw_pcie_host_init(&pci->pp); in kirin_pcie_probe()
774 .name = "kirin-pcie",
782 MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs");