Lines Matching +full:pcie +full:- +full:phy +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
22 #include <linux/phy/phy.h>
29 #define BRCFG_PCIE_RX0 0x00000000
30 #define BRCFG_PCIE_RX1 0x00000004
31 #define BRCFG_INTERRUPT 0x00000010
32 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
34 /* Egress - Bridge translation registers */
35 #define E_BREG_CAPABILITIES 0x00000200
36 #define E_BREG_CONTROL 0x00000208
37 #define E_BREG_BASE_LO 0x00000210
38 #define E_BREG_BASE_HI 0x00000214
39 #define E_ECAM_CAPABILITIES 0x00000220
40 #define E_ECAM_CONTROL 0x00000228
41 #define E_ECAM_BASE_LO 0x00000230
42 #define E_ECAM_BASE_HI 0x00000234
44 /* Ingress - address translations */
45 #define I_MSII_CAPABILITIES 0x00000300
46 #define I_MSII_CONTROL 0x00000308
47 #define I_MSII_BASE_LO 0x00000310
48 #define I_MSII_BASE_HI 0x00000314
50 #define I_ISUB_CONTROL 0x000003E8
51 #define SET_ISUB_CONTROL BIT(0)
52 /* Rxed msg fifo - Interrupt status registers */
53 #define MSGF_MISC_STATUS 0x00000400
54 #define MSGF_MISC_MASK 0x00000404
55 #define MSGF_LEG_STATUS 0x00000420
56 #define MSGF_LEG_MASK 0x00000424
57 #define MSGF_MSI_STATUS_LO 0x00000440
58 #define MSGF_MSI_STATUS_HI 0x00000444
59 #define MSGF_MSI_MASK_LO 0x00000448
60 #define MSGF_MSI_MASK_HI 0x0000044C
71 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
104 #define MSGF_LEG_SR_INTA BIT(0)
112 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
113 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
115 #define MSII_PRESENT BIT(0)
116 #define MSII_ENABLE BIT(0)
120 #define BRCFG_INTERRUPT_MASK BIT(0)
121 #define BREG_PRESENT BIT(0)
122 #define BREG_ENABLE BIT(0)
126 #define E_ECAM_PRESENT BIT(0)
127 #define E_ECAM_CR_ENABLE BIT(0)
132 #define CFG_DMA_REG_BAR GENMASK(2, 0)
133 #define CFG_PCIE_CACHE GENMASK(7, 0)
138 #define PS_LINKUP_OFFSET 0x00000238
139 #define PCIE_PHY_LINKUP_BIT BIT(0)
161 struct phy *phy[4]; member
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { in nwl_wait_for_link()
207 if (nwl_phy_link_up(pcie)) in nwl_wait_for_link()
208 return 0; in nwl_wait_for_link()
212 dev_err(dev, "PHY link never came up\n"); in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device() local
222 if (!nwl_pcie_link_up(pcie)) in nwl_pcie_valid_device()
224 } else if (devfn > 0) in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus() local
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
252 /* PCIe operations */
261 struct nwl_pcie *pcie = data; in nwl_pcie_misc_handler() local
262 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_misc_handler()
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
319 struct nwl_pcie *pcie; in nwl_pcie_leg_handler() local
324 pcie = irq_desc_get_handler_data(desc); in nwl_pcie_leg_handler()
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_leg_handler()
327 MSGF_LEG_SR_MASKALL) != 0) { in nwl_pcie_leg_handler()
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in nwl_pcie_leg_handler()
335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) in nwl_pcie_handle_msi_irq() argument
337 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { in nwl_pcie_handle_msi_irq()
343 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
344 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_high() local
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); in nwl_pcie_msi_handler_high()
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_low() local
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); in nwl_pcie_msi_handler_low()
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_mask_intx_irq() local
376 mask = 1 << data->hwirq; in nwl_mask_intx_irq()
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_mask_intx_irq()
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_intx_irq()
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_unmask_intx_irq() local
390 mask = 1 << data->hwirq; in nwl_unmask_intx_irq()
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_unmask_intx_irq()
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_intx_irq()
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
409 irq_set_chip_data(irq, domain->host_data); in nwl_intx_map()
412 return 0; in nwl_intx_map()
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_compose_msi_msg() local
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
441 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
442 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
443 msg->data = data->hwirq; in nwl_compose_msi_msg()
454 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc() local
455 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
459 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
460 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
462 if (bit < 0) { in nwl_irq_domain_alloc()
463 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
464 return -ENOSPC; in nwl_irq_domain_alloc()
467 for (i = 0; i < nr_irqs; i++) { in nwl_irq_domain_alloc()
469 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
472 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
473 return 0; in nwl_irq_domain_alloc()
480 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_irq_domain_free() local
481 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
483 mutex_lock(&msi->lock); in nwl_irq_domain_free()
484 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
486 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
494 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_msi_irq_domain() argument
497 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
498 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
499 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
501 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
502 &dev_msi_domain_ops, pcie); in nwl_pcie_init_msi_irq_domain()
503 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
505 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
507 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
509 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
510 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
512 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
513 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
516 return 0; in nwl_pcie_init_msi_irq_domain()
519 static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i) in nwl_pcie_phy_power_off() argument
521 int err = phy_power_off(pcie->phy[i]); in nwl_pcie_phy_power_off()
524 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i, in nwl_pcie_phy_power_off()
528 static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i) in nwl_pcie_phy_exit() argument
530 int err = phy_exit(pcie->phy[i]); in nwl_pcie_phy_exit()
533 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err); in nwl_pcie_phy_exit()
536 static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) in nwl_pcie_phy_enable() argument
540 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_phy_enable()
541 ret = phy_init(pcie->phy[i]); in nwl_pcie_phy_enable()
545 ret = phy_power_on(pcie->phy[i]); in nwl_pcie_phy_enable()
547 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_enable()
552 return 0; in nwl_pcie_phy_enable()
555 while (i--) { in nwl_pcie_phy_enable()
556 nwl_pcie_phy_power_off(pcie, i); in nwl_pcie_phy_enable()
557 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_enable()
563 static void nwl_pcie_phy_disable(struct nwl_pcie *pcie) in nwl_pcie_phy_disable() argument
567 for (i = ARRAY_SIZE(pcie->phy); i--;) { in nwl_pcie_phy_disable()
568 nwl_pcie_phy_power_off(pcie, i); in nwl_pcie_phy_disable()
569 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_disable()
573 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_irq_domain() argument
575 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
576 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
582 return -EINVAL; in nwl_pcie_init_irq_domain()
585 pcie->intx_irq_domain = irq_domain_add_linear(intc_node, in nwl_pcie_init_irq_domain()
588 pcie); in nwl_pcie_init_irq_domain()
590 if (!pcie->intx_irq_domain) { in nwl_pcie_init_irq_domain()
592 return -ENOMEM; in nwl_pcie_init_irq_domain()
595 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
596 nwl_pcie_init_msi_irq_domain(pcie); in nwl_pcie_init_irq_domain()
597 return 0; in nwl_pcie_init_irq_domain()
600 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) in nwl_pcie_enable_msi() argument
602 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
604 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
608 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
611 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
612 if (msi->irq_msi1 < 0) in nwl_pcie_enable_msi()
613 return -EINVAL; in nwl_pcie_enable_msi()
615 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
616 nwl_pcie_msi_handler_high, pcie); in nwl_pcie_enable_msi()
619 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
620 if (msi->irq_msi0 < 0) in nwl_pcie_enable_msi()
621 return -EINVAL; in nwl_pcie_enable_msi()
623 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
624 nwl_pcie_msi_handler_low, pcie); in nwl_pcie_enable_msi()
627 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; in nwl_pcie_enable_msi()
630 return -EIO; in nwl_pcie_enable_msi()
634 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
638 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
642 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
643 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
644 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
650 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
652 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
655 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
661 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
663 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
666 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
668 return 0; in nwl_pcie_enable_msi()
671 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) in nwl_pcie_bridge_init() argument
673 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
678 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; in nwl_pcie_bridge_init()
685 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
687 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
691 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
695 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
699 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
702 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
705 /* This routes the PCIe DMA traffic to go through CCI path */ in nwl_pcie_bridge_init()
706 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
707 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | in nwl_pcie_bridge_init()
710 err = nwl_wait_for_link(pcie); in nwl_pcie_bridge_init()
714 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; in nwl_pcie_bridge_init()
721 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
724 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
730 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
733 if (nwl_pcie_link_up(pcie)) in nwl_pcie_bridge_init()
739 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
740 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
741 return -EINVAL; in nwl_pcie_bridge_init()
743 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
745 "nwl_pcie:misc", pcie); in nwl_pcie_bridge_init()
748 pcie->irq_misc); in nwl_pcie_bridge_init()
753 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
756 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
760 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
763 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
766 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
770 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
773 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()
776 return 0; in nwl_pcie_bridge_init()
779 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, in nwl_pcie_parse_dt() argument
782 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
787 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
788 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
789 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
790 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
793 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
794 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
795 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
796 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
799 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
800 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
801 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
802 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
805 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
806 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
807 return pcie->irq_intx; in nwl_pcie_parse_dt()
809 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
810 nwl_pcie_leg_handler, pcie); in nwl_pcie_parse_dt()
813 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_parse_dt()
814 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); in nwl_pcie_parse_dt()
815 if (PTR_ERR(pcie->phy[i]) == -ENODEV) { in nwl_pcie_parse_dt()
816 pcie->phy[i] = NULL; in nwl_pcie_parse_dt()
820 if (IS_ERR(pcie->phy[i])) in nwl_pcie_parse_dt()
821 return PTR_ERR(pcie->phy[i]); in nwl_pcie_parse_dt()
824 return 0; in nwl_pcie_parse_dt()
828 { .compatible = "xlnx,nwl-pcie-2.11", },
834 struct device *dev = &pdev->dev; in nwl_pcie_probe()
835 struct nwl_pcie *pcie; in nwl_pcie_probe() local
839 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in nwl_pcie_probe()
841 return -ENODEV; in nwl_pcie_probe()
843 pcie = pci_host_bridge_priv(bridge); in nwl_pcie_probe()
844 platform_set_drvdata(pdev, pcie); in nwl_pcie_probe()
846 pcie->dev = dev; in nwl_pcie_probe()
848 err = nwl_pcie_parse_dt(pcie, pdev); in nwl_pcie_probe()
854 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
855 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
856 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
858 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
860 dev_err(dev, "can't enable PCIe ref clock\n"); in nwl_pcie_probe()
864 err = nwl_pcie_phy_enable(pcie); in nwl_pcie_probe()
870 err = nwl_pcie_bridge_init(pcie); in nwl_pcie_probe()
876 err = nwl_pcie_init_irq_domain(pcie); in nwl_pcie_probe()
882 bridge->sysdata = pcie; in nwl_pcie_probe()
883 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
886 err = nwl_pcie_enable_msi(pcie); in nwl_pcie_probe()
887 if (err < 0) { in nwl_pcie_probe()
895 return 0; in nwl_pcie_probe()
898 nwl_pcie_phy_disable(pcie); in nwl_pcie_probe()
900 clk_disable_unprepare(pcie->clk); in nwl_pcie_probe()
906 struct nwl_pcie *pcie = platform_get_drvdata(pdev); in nwl_pcie_remove() local
908 nwl_pcie_phy_disable(pcie); in nwl_pcie_remove()
909 clk_disable_unprepare(pcie->clk); in nwl_pcie_remove()
914 .name = "nwl-pcie",