Lines Matching +full:pcie +full:- +full:phy +full:- +full:0

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
10   - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13   "#phy-cells":
15     description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19       - lantiq,vrx200-pcie-phy
20       - lantiq,arx300-pcie-phy
27       - description: PHY module clock
28       - description: PDI register clock
30   clock-names:
32       - const: phy
33       - const: pdi
37       - description: exclusive PHY reset line
38       - description: shared reset line between the PCIe PHY and PCIe controller
40   reset-names:
42       - const: phy
43       - const: pcie
49   lantiq,rcu-endian-offset:
51     description: the offset of the endian registers for this PHY instance in the RCU syscon
53   lantiq,rcu-big-endian-mask:
55     description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
57   big-endian:
58     description: Configures the PDI (PHY) registers in big-endian mode
61   little-endian:
62     description: Configures the PDI (PHY) registers in big-endian mode
66   - "#phy-cells"
67   - compatible
68   - reg
69   - clocks
70   - clock-names
71   - resets
72   - reset-names
73   - lantiq,rcu
74   - lantiq,rcu-endian-offset
75   - lantiq,rcu-big-endian-mask
80   - |
81     pcie0_phy: phy@106800 {
82         compatible = "lantiq,vrx200-pcie-phy";
83         reg = <0x106800 0x100>;
85         lantiq,rcu-endian-offset = <0x4c>;
86         lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
87         big-endian;
89         clock-names = "phy", "pdi";
91         reset-names = "phy", "pcie";
92         #phy-cells = <1>;