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Searched +full:opp +full:- +full:microvolt +full:- +full:speed (Results 1 – 25 of 46) sorted by relevance

12

/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk3576.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: regulator-ppvar-sys {
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dimx-cpufreq-dt.txt1 i.MX CPUFreq-DT OPP bindings
5 "speed grading" value which are written in fuses. These bits are combined with
6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
9 --------------------
11 For each opp entry in 'operating-points-v2' table:
12 - opp-supported-hw: Two bitmaps indicating:
13 - Supported speed grade mask
14 - Supported market segment mask
21 --------
24 compatible = "operating-points-v2";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-innocomm-wb15.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_regulator>;
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-name = "epdev_on";
18 enable-active-high;
[all …]
H A Dimx8mn-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "imx8mn-overdrive.dtsi"
16 compatible = "mmc-pwrseq-simple";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
19 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
21 clock-names = "ext_clock";
22 post-power-on-delay-ms = <80>;
32 cpu-supply = <&buck2_reg>;
36 cpu-supply = <&buck2_reg>;
[all …]
H A Dimx8mm-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "imx8mm-overdrive.dtsi"
15 compatible = "mmc-pwrseq-simple";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
18 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
20 clock-names = "ext_clock";
21 post-power-on-delay-ms = <80>;
31 cpu-supply = <&buck2_reg>;
35 cpu-supply = <&buck2_reg>;
[all …]
H A Dimx8mp-skov-reva.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "imx8mp-nominal.dtsi"
6 #include <dt-bindings/leds/common.h>
27 compatible = "pwm-backlight";
28 pinctrl-0 = <&pinctrl_backlight>;
30 power-supply = <&reg_24v>;
31 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
32 brightness-levels = <0 255>;
33 num-interpolated-steps = <17>;
34 default-brightness-level = <8>;
[all …]
H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
32 stdout-path = &uart2;
40 gpio-keys {
41 compatible = "gpio-keys";
[all …]
H A Dimx8mq-librem5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-bindings/pwm/pwm.h"
12 #include "dt-bindings/usb/pd.h"
18 chassis-type = "handset";
20 backlight_dsi: backlight-dsi {
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap34xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
[all …]
/linux/Documentation/devicetree/bindings/gpu/
H A Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - items:
19 - enum:
20 - allwinner,sun50i-h616-mali
21 - amlogic,meson-g12a-mali
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal-net";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 u-boot {
22 compatible = "u-boot,config";
23 bootscr-address = /bits/ 64 <0x20000000>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-lg-x3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/mfd/max77620.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cpu-opp.dtsi"
11 #include "tegra30-cpu-opp-microvolt.dtsi"
14 chassis-type = "handset";
30 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
[all …]
H A Dtegra30-asus-p1801-t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
13 model = "Asus Portable AiO P1801-T";
14 compatible = "asus,p1801-t", "nvidia,tegra30";
15 chassis-type = "convertible";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq6018.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&intc>;
20 sleep_clk: sleep-clk {
[all …]
H A Dipq5018.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
11 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-v40-bananapi-m2-berry.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun8i-r40.dtsi"
45 #include "sun8i-r40-cpu-opp.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
51 compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
59 stdout-path = "serial0:115200n8";
63 compatible = "hdmi-connector";
68 remote-endpoint = <&hdmi_out_con>;
74 compatible = "gpio-leds";
[all …]

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