1*c47d7b73SSascha Hauer// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*c47d7b73SSascha Hauer/* 3*c47d7b73SSascha Hauer * Copyright 2018 Bang & Olufsen 4*c47d7b73SSascha Hauer */ 5*c47d7b73SSascha Hauer 6*c47d7b73SSascha Hauer#include "imx8mm.dtsi" 7*c47d7b73SSascha Hauer#include <dt-bindings/phy/phy-imx8-pcie.h> 8*c47d7b73SSascha Hauer 9*c47d7b73SSascha Hauer/ { 10*c47d7b73SSascha Hauer reg_modem: regulator-modem { 11*c47d7b73SSascha Hauer compatible = "regulator-fixed"; 12*c47d7b73SSascha Hauer pinctrl-names = "default"; 13*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_modem_regulator>; 14*c47d7b73SSascha Hauer regulator-min-microvolt = <3300000>; 15*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 16*c47d7b73SSascha Hauer regulator-name = "epdev_on"; 17*c47d7b73SSascha Hauer gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; 18*c47d7b73SSascha Hauer enable-active-high; 19*c47d7b73SSascha Hauer regulator-always-on; 20*c47d7b73SSascha Hauer }; 21*c47d7b73SSascha Hauer 22*c47d7b73SSascha Hauer reg_3v3_out: regulator-3v3-out { 23*c47d7b73SSascha Hauer compatible = "regulator-fixed"; 24*c47d7b73SSascha Hauer regulator-name = "3V3_OUT"; 25*c47d7b73SSascha Hauer regulator-min-microvolt = <3300000>; 26*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 27*c47d7b73SSascha Hauer }; 28*c47d7b73SSascha Hauer}; 29*c47d7b73SSascha Hauer 30*c47d7b73SSascha Hauer&cpu_alert0 { 31*c47d7b73SSascha Hauer temperature = <95000>; 32*c47d7b73SSascha Hauer}; 33*c47d7b73SSascha Hauer 34*c47d7b73SSascha Hauer&cpu_crit0 { 35*c47d7b73SSascha Hauer temperature = <105000>; 36*c47d7b73SSascha Hauer}; 37*c47d7b73SSascha Hauer 38*c47d7b73SSascha Hauer&ddrc { 39*c47d7b73SSascha Hauer operating-points-v2 = <&ddrc_opp_table>; 40*c47d7b73SSascha Hauer 41*c47d7b73SSascha Hauer ddrc_opp_table: opp-table { 42*c47d7b73SSascha Hauer compatible = "operating-points-v2"; 43*c47d7b73SSascha Hauer 44*c47d7b73SSascha Hauer opp-25000000 { 45*c47d7b73SSascha Hauer opp-hz = /bits/ 64 <25000000>; 46*c47d7b73SSascha Hauer }; 47*c47d7b73SSascha Hauer 48*c47d7b73SSascha Hauer opp-100000000 { 49*c47d7b73SSascha Hauer opp-hz = /bits/ 64 <100000000>; 50*c47d7b73SSascha Hauer }; 51*c47d7b73SSascha Hauer 52*c47d7b73SSascha Hauer opp-600000000 { 53*c47d7b73SSascha Hauer opp-hz = /bits/ 64 <600000000>; 54*c47d7b73SSascha Hauer }; 55*c47d7b73SSascha Hauer }; 56*c47d7b73SSascha Hauer}; 57*c47d7b73SSascha Hauer 58*c47d7b73SSascha Hauer&i2c1 { 59*c47d7b73SSascha Hauer clock-frequency = <100000>; 60*c47d7b73SSascha Hauer pinctrl-names = "default", "gpio"; 61*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_i2c1>; 62*c47d7b73SSascha Hauer pinctrl-1 = <&pinctrl_i2c1_gpio>; 63*c47d7b73SSascha Hauer scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64*c47d7b73SSascha Hauer sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 65*c47d7b73SSascha Hauer status = "okay"; 66*c47d7b73SSascha Hauer 67*c47d7b73SSascha Hauer pmic@4b { 68*c47d7b73SSascha Hauer compatible = "rohm,bd71847"; 69*c47d7b73SSascha Hauer reg = <0x4b>; 70*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_pmic>; 71*c47d7b73SSascha Hauer interrupt-parent = <&gpio1>; 72*c47d7b73SSascha Hauer interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 73*c47d7b73SSascha Hauer rohm,reset-snvs-powered; 74*c47d7b73SSascha Hauer 75*c47d7b73SSascha Hauer regulators { 76*c47d7b73SSascha Hauer buck1_reg: BUCK1 { 77*c47d7b73SSascha Hauer regulator-name = "buck1"; 78*c47d7b73SSascha Hauer regulator-min-microvolt = <700000>; 79*c47d7b73SSascha Hauer regulator-max-microvolt = <1300000>; 80*c47d7b73SSascha Hauer regulator-boot-on; 81*c47d7b73SSascha Hauer regulator-always-on; 82*c47d7b73SSascha Hauer regulator-ramp-delay = <1250>; 83*c47d7b73SSascha Hauer rohm,dvs-run-voltage = <850000>; 84*c47d7b73SSascha Hauer rohm,dvs-idle-voltage = <850000>; 85*c47d7b73SSascha Hauer rohm,dvs-suspend-voltage = <850000>; 86*c47d7b73SSascha Hauer }; 87*c47d7b73SSascha Hauer 88*c47d7b73SSascha Hauer buck2_reg: BUCK2 { 89*c47d7b73SSascha Hauer regulator-name = "buck2"; 90*c47d7b73SSascha Hauer regulator-min-microvolt = <700000>; 91*c47d7b73SSascha Hauer regulator-max-microvolt = <1300000>; 92*c47d7b73SSascha Hauer regulator-boot-on; 93*c47d7b73SSascha Hauer regulator-always-on; 94*c47d7b73SSascha Hauer regulator-ramp-delay = <1250>; 95*c47d7b73SSascha Hauer rohm,dvs-run-voltage = <1000000>; 96*c47d7b73SSascha Hauer rohm,dvs-idle-voltage = <900000>; 97*c47d7b73SSascha Hauer }; 98*c47d7b73SSascha Hauer 99*c47d7b73SSascha Hauer buck3_reg: BUCK3 { 100*c47d7b73SSascha Hauer // buck5 in datasheet 101*c47d7b73SSascha Hauer regulator-name = "buck3"; 102*c47d7b73SSascha Hauer regulator-min-microvolt = <700000>; 103*c47d7b73SSascha Hauer regulator-max-microvolt = <1350000>; 104*c47d7b73SSascha Hauer regulator-boot-on; 105*c47d7b73SSascha Hauer regulator-always-on; 106*c47d7b73SSascha Hauer }; 107*c47d7b73SSascha Hauer 108*c47d7b73SSascha Hauer buck4_reg: BUCK4 { 109*c47d7b73SSascha Hauer // buck6 in datasheet 110*c47d7b73SSascha Hauer regulator-name = "buck4"; 111*c47d7b73SSascha Hauer regulator-min-microvolt = <3000000>; 112*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 113*c47d7b73SSascha Hauer regulator-boot-on; 114*c47d7b73SSascha Hauer regulator-always-on; 115*c47d7b73SSascha Hauer }; 116*c47d7b73SSascha Hauer 117*c47d7b73SSascha Hauer buck5_reg: BUCK5 { 118*c47d7b73SSascha Hauer // buck7 in datasheet 119*c47d7b73SSascha Hauer regulator-name = "buck5"; 120*c47d7b73SSascha Hauer regulator-min-microvolt = <1605000>; 121*c47d7b73SSascha Hauer regulator-max-microvolt = <1995000>; 122*c47d7b73SSascha Hauer regulator-boot-on; 123*c47d7b73SSascha Hauer regulator-always-on; 124*c47d7b73SSascha Hauer }; 125*c47d7b73SSascha Hauer 126*c47d7b73SSascha Hauer buck6_reg: BUCK6 { 127*c47d7b73SSascha Hauer // buck8 in datasheet 128*c47d7b73SSascha Hauer regulator-name = "buck6"; 129*c47d7b73SSascha Hauer regulator-min-microvolt = <800000>; 130*c47d7b73SSascha Hauer regulator-max-microvolt = <1400000>; 131*c47d7b73SSascha Hauer regulator-boot-on; 132*c47d7b73SSascha Hauer regulator-always-on; 133*c47d7b73SSascha Hauer }; 134*c47d7b73SSascha Hauer 135*c47d7b73SSascha Hauer ldo1_reg: LDO1 { 136*c47d7b73SSascha Hauer regulator-name = "ldo1"; 137*c47d7b73SSascha Hauer regulator-min-microvolt = <1800000>; 138*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 139*c47d7b73SSascha Hauer regulator-boot-on; 140*c47d7b73SSascha Hauer regulator-always-on; 141*c47d7b73SSascha Hauer }; 142*c47d7b73SSascha Hauer 143*c47d7b73SSascha Hauer ldo2_reg: LDO2 { 144*c47d7b73SSascha Hauer regulator-name = "ldo2"; 145*c47d7b73SSascha Hauer regulator-min-microvolt = <800000>; 146*c47d7b73SSascha Hauer regulator-max-microvolt = <900000>; 147*c47d7b73SSascha Hauer regulator-boot-on; 148*c47d7b73SSascha Hauer regulator-always-on; 149*c47d7b73SSascha Hauer }; 150*c47d7b73SSascha Hauer 151*c47d7b73SSascha Hauer ldo3_reg: LDO3 { 152*c47d7b73SSascha Hauer regulator-name = "ldo3"; 153*c47d7b73SSascha Hauer regulator-min-microvolt = <1800000>; 154*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 155*c47d7b73SSascha Hauer regulator-boot-on; 156*c47d7b73SSascha Hauer regulator-always-on; 157*c47d7b73SSascha Hauer }; 158*c47d7b73SSascha Hauer 159*c47d7b73SSascha Hauer ldo4_reg: LDO4 { 160*c47d7b73SSascha Hauer regulator-name = "ldo4"; 161*c47d7b73SSascha Hauer regulator-min-microvolt = <900000>; 162*c47d7b73SSascha Hauer regulator-max-microvolt = <1800000>; 163*c47d7b73SSascha Hauer regulator-boot-on; 164*c47d7b73SSascha Hauer regulator-always-on; 165*c47d7b73SSascha Hauer }; 166*c47d7b73SSascha Hauer 167*c47d7b73SSascha Hauer ldo5_reg: LDO5 { 168*c47d7b73SSascha Hauer regulator-name = "ldo5"; 169*c47d7b73SSascha Hauer regulator-min-microvolt = <1800000>; 170*c47d7b73SSascha Hauer regulator-max-microvolt = <3300000>; 171*c47d7b73SSascha Hauer }; 172*c47d7b73SSascha Hauer 173*c47d7b73SSascha Hauer ldo6_reg: LDO6 { 174*c47d7b73SSascha Hauer regulator-name = "ldo6"; 175*c47d7b73SSascha Hauer regulator-min-microvolt = <900000>; 176*c47d7b73SSascha Hauer regulator-max-microvolt = <1800000>; 177*c47d7b73SSascha Hauer regulator-boot-on; 178*c47d7b73SSascha Hauer regulator-always-on; 179*c47d7b73SSascha Hauer }; 180*c47d7b73SSascha Hauer }; 181*c47d7b73SSascha Hauer }; 182*c47d7b73SSascha Hauer}; 183*c47d7b73SSascha Hauer 184*c47d7b73SSascha Hauer&i2c2 { 185*c47d7b73SSascha Hauer clock-frequency = <100000>; 186*c47d7b73SSascha Hauer pinctrl-names = "default", "gpio"; 187*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_i2c2>; 188*c47d7b73SSascha Hauer pinctrl-1 = <&pinctrl_i2c2_gpio>; 189*c47d7b73SSascha Hauer scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 190*c47d7b73SSascha Hauer sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 191*c47d7b73SSascha Hauer status = "okay"; 192*c47d7b73SSascha Hauer}; 193*c47d7b73SSascha Hauer 194*c47d7b73SSascha Hauer&i2c3 { 195*c47d7b73SSascha Hauer pinctrl-names = "default", "gpio"; 196*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_i2c3>; 197*c47d7b73SSascha Hauer pinctrl-1 = <&pinctrl_i2c3_gpio>; 198*c47d7b73SSascha Hauer scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 199*c47d7b73SSascha Hauer sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 200*c47d7b73SSascha Hauer}; 201*c47d7b73SSascha Hauer 202*c47d7b73SSascha Hauer&pcie_phy { 203*c47d7b73SSascha Hauer fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 204*c47d7b73SSascha Hauer fsl,tx-deemph-gen1 = <0x2d>; 205*c47d7b73SSascha Hauer fsl,tx-deemph-gen2 = <0xf>; 206*c47d7b73SSascha Hauer status = "okay"; 207*c47d7b73SSascha Hauer}; 208*c47d7b73SSascha Hauer 209*c47d7b73SSascha Hauer&pcie0 { 210*c47d7b73SSascha Hauer pinctrl-names = "default"; 211*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_pcie0>; 212*c47d7b73SSascha Hauer reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; 213*c47d7b73SSascha Hauer fsl,max-link-speed = <1>; 214*c47d7b73SSascha Hauer assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; 215*c47d7b73SSascha Hauer assigned-clock-rates = <10000000>, <250000000>; 216*c47d7b73SSascha Hauer assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; 217*c47d7b73SSascha Hauer status = "okay"; 218*c47d7b73SSascha Hauer}; 219*c47d7b73SSascha Hauer 220*c47d7b73SSascha Hauer&uart1 { /* BT */ 221*c47d7b73SSascha Hauer pinctrl-names = "default"; 222*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_uart1>; 223*c47d7b73SSascha Hauer assigned-clocks = <&clk IMX8MM_CLK_UART1>; 224*c47d7b73SSascha Hauer assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 225*c47d7b73SSascha Hauer uart-has-rtscts; 226*c47d7b73SSascha Hauer status = "okay"; 227*c47d7b73SSascha Hauer 228*c47d7b73SSascha Hauer bluetooth { 229*c47d7b73SSascha Hauer compatible = "brcm,bcm4349-bt"; 230*c47d7b73SSascha Hauer pinctrl-names = "default"; 231*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_modem_bt>; 232*c47d7b73SSascha Hauer device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 233*c47d7b73SSascha Hauer host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; 234*c47d7b73SSascha Hauer shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; 235*c47d7b73SSascha Hauer vbat-supply = <®_3v3_out>; 236*c47d7b73SSascha Hauer vddio-supply = <®_3v3_out>; 237*c47d7b73SSascha Hauer clocks = <&osc_32k>; 238*c47d7b73SSascha Hauer max-speed = <3000000>; 239*c47d7b73SSascha Hauer clock-names = "extclk"; 240*c47d7b73SSascha Hauer }; 241*c47d7b73SSascha Hauer}; 242*c47d7b73SSascha Hauer 243*c47d7b73SSascha Hauer&uart2 { /* console */ 244*c47d7b73SSascha Hauer pinctrl-names = "default"; 245*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_uart2>; 246*c47d7b73SSascha Hauer}; 247*c47d7b73SSascha Hauer 248*c47d7b73SSascha Hauer&usdhc1 { 249*c47d7b73SSascha Hauer pinctrl-names = "default"; 250*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_usdhc1>; 251*c47d7b73SSascha Hauer bus-width = <8>; 252*c47d7b73SSascha Hauer no-sd; 253*c47d7b73SSascha Hauer no-sdio; 254*c47d7b73SSascha Hauer non-removable; 255*c47d7b73SSascha Hauer status = "okay"; 256*c47d7b73SSascha Hauer}; 257*c47d7b73SSascha Hauer 258*c47d7b73SSascha Hauer&usdhc2 { 259*c47d7b73SSascha Hauer pinctrl-names = "default", "state_100mhz", "state_200mhz"; 260*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 261*c47d7b73SSascha Hauer pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 262*c47d7b73SSascha Hauer pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 263*c47d7b73SSascha Hauer bus-width = <4>; 264*c47d7b73SSascha Hauer}; 265*c47d7b73SSascha Hauer 266*c47d7b73SSascha Hauer&wdog1 { 267*c47d7b73SSascha Hauer pinctrl-names = "default"; 268*c47d7b73SSascha Hauer pinctrl-0 = <&pinctrl_wdog>; 269*c47d7b73SSascha Hauer fsl,ext-reset-output; 270*c47d7b73SSascha Hauer status = "okay"; 271*c47d7b73SSascha Hauer}; 272*c47d7b73SSascha Hauer 273*c47d7b73SSascha Hauer&A53_0 { 274*c47d7b73SSascha Hauer cpu-supply = <&buck2_reg>; 275*c47d7b73SSascha Hauer}; 276*c47d7b73SSascha Hauer 277*c47d7b73SSascha Hauer&A53_1 { 278*c47d7b73SSascha Hauer cpu-supply = <&buck2_reg>; 279*c47d7b73SSascha Hauer}; 280*c47d7b73SSascha Hauer 281*c47d7b73SSascha Hauer&A53_2 { 282*c47d7b73SSascha Hauer cpu-supply = <&buck2_reg>; 283*c47d7b73SSascha Hauer}; 284*c47d7b73SSascha Hauer 285*c47d7b73SSascha Hauer&A53_3 { 286*c47d7b73SSascha Hauer cpu-supply = <&buck2_reg>; 287*c47d7b73SSascha Hauer}; 288*c47d7b73SSascha Hauer 289*c47d7b73SSascha Hauer/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */ 290*c47d7b73SSascha Hauer 291*c47d7b73SSascha Hauer&iomuxc { 292*c47d7b73SSascha Hauer pinctrl_i2c1: i2c1-grp { 293*c47d7b73SSascha Hauer fsl,pins = < 294*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 295*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 296*c47d7b73SSascha Hauer >; 297*c47d7b73SSascha Hauer }; 298*c47d7b73SSascha Hauer 299*c47d7b73SSascha Hauer pinctrl_i2c1_gpio: i2c1-gpio-grp { 300*c47d7b73SSascha Hauer fsl,pins = < 301*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 302*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 303*c47d7b73SSascha Hauer >; 304*c47d7b73SSascha Hauer }; 305*c47d7b73SSascha Hauer 306*c47d7b73SSascha Hauer pinctrl_i2c2: i2c2-grp { 307*c47d7b73SSascha Hauer fsl,pins = < 308*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 309*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 310*c47d7b73SSascha Hauer >; 311*c47d7b73SSascha Hauer }; 312*c47d7b73SSascha Hauer 313*c47d7b73SSascha Hauer pinctrl_i2c2_gpio: i2c2-gpio-grp { 314*c47d7b73SSascha Hauer fsl,pins = < 315*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 316*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 317*c47d7b73SSascha Hauer >; 318*c47d7b73SSascha Hauer }; 319*c47d7b73SSascha Hauer 320*c47d7b73SSascha Hauer pinctrl_i2c3: i2c3-grp { 321*c47d7b73SSascha Hauer fsl,pins = < 322*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 323*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 324*c47d7b73SSascha Hauer >; 325*c47d7b73SSascha Hauer }; 326*c47d7b73SSascha Hauer 327*c47d7b73SSascha Hauer pinctrl_i2c3_gpio: i2c3-gpio-grp { 328*c47d7b73SSascha Hauer fsl,pins = < 329*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 330*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 331*c47d7b73SSascha Hauer >; 332*c47d7b73SSascha Hauer }; 333*c47d7b73SSascha Hauer 334*c47d7b73SSascha Hauer pinctrl_pcie0: pcie0-grp { 335*c47d7b73SSascha Hauer fsl,pins = < 336*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 337*c47d7b73SSascha Hauer MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6 338*c47d7b73SSascha Hauer >; 339*c47d7b73SSascha Hauer }; 340*c47d7b73SSascha Hauer 341*c47d7b73SSascha Hauer pinctrl_modem_bt: modem-bt-grp { 342*c47d7b73SSascha Hauer fsl,pins = < 343*c47d7b73SSascha Hauer MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 344*c47d7b73SSascha Hauer MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19 345*c47d7b73SSascha Hauer MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 346*c47d7b73SSascha Hauer MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 347*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 348*c47d7b73SSascha Hauer >; 349*c47d7b73SSascha Hauer }; 350*c47d7b73SSascha Hauer 351*c47d7b73SSascha Hauer pinctrl_modem_regulator: modem-reg-grp { 352*c47d7b73SSascha Hauer fsl,pins = < 353*c47d7b73SSascha Hauer MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41 354*c47d7b73SSascha Hauer >; 355*c47d7b73SSascha Hauer }; 356*c47d7b73SSascha Hauer 357*c47d7b73SSascha Hauer pinctrl_pmic: pmic-irq-grp { 358*c47d7b73SSascha Hauer fsl,pins = < 359*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 360*c47d7b73SSascha Hauer >; 361*c47d7b73SSascha Hauer }; 362*c47d7b73SSascha Hauer 363*c47d7b73SSascha Hauer pinctrl_uart1: uart1-grp { 364*c47d7b73SSascha Hauer fsl,pins = < 365*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 366*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 367*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 368*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 369*c47d7b73SSascha Hauer >; 370*c47d7b73SSascha Hauer }; 371*c47d7b73SSascha Hauer 372*c47d7b73SSascha Hauer pinctrl_uart2: uart2-grp { 373*c47d7b73SSascha Hauer fsl,pins = < 374*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 375*c47d7b73SSascha Hauer MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 376*c47d7b73SSascha Hauer >; 377*c47d7b73SSascha Hauer }; 378*c47d7b73SSascha Hauer 379*c47d7b73SSascha Hauer pinctrl_usdhc1: usdhc1-grp { 380*c47d7b73SSascha Hauer fsl,pins = < 381*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190 382*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 383*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 384*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 385*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 386*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 387*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 388*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 389*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 390*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 391*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 392*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0 393*c47d7b73SSascha Hauer >; 394*c47d7b73SSascha Hauer }; 395*c47d7b73SSascha Hauer 396*c47d7b73SSascha Hauer pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 397*c47d7b73SSascha Hauer fsl,pins = < 398*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194 399*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 400*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 401*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 402*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 403*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 404*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 405*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 406*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 407*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 408*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 409*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4 410*c47d7b73SSascha Hauer >; 411*c47d7b73SSascha Hauer }; 412*c47d7b73SSascha Hauer 413*c47d7b73SSascha Hauer pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 414*c47d7b73SSascha Hauer fsl,pins = < 415*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196 416*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 417*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 418*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 419*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 420*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 421*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 422*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 423*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 424*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 425*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 426*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6 427*c47d7b73SSascha Hauer >; 428*c47d7b73SSascha Hauer }; 429*c47d7b73SSascha Hauer 430*c47d7b73SSascha Hauer pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 431*c47d7b73SSascha Hauer fsl,pins = < 432*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0 433*c47d7b73SSascha Hauer >; 434*c47d7b73SSascha Hauer }; 435*c47d7b73SSascha Hauer 436*c47d7b73SSascha Hauer pinctrl_usdhc2: usdhc2-grp { 437*c47d7b73SSascha Hauer fsl,pins = < 438*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 439*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 440*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 441*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 442*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 443*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 444*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 445*c47d7b73SSascha Hauer >; 446*c47d7b73SSascha Hauer }; 447*c47d7b73SSascha Hauer 448*c47d7b73SSascha Hauer pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 449*c47d7b73SSascha Hauer fsl,pins = < 450*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 451*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 452*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 453*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 454*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 455*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 456*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 457*c47d7b73SSascha Hauer >; 458*c47d7b73SSascha Hauer }; 459*c47d7b73SSascha Hauer 460*c47d7b73SSascha Hauer pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 461*c47d7b73SSascha Hauer fsl,pins = < 462*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 463*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 464*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 465*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 466*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 467*c47d7b73SSascha Hauer MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 468*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 469*c47d7b73SSascha Hauer >; 470*c47d7b73SSascha Hauer }; 471*c47d7b73SSascha Hauer 472*c47d7b73SSascha Hauer pinctrl_wdog: wdog-grp { 473*c47d7b73SSascha Hauer fsl,pins = < 474*c47d7b73SSascha Hauer MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 475*c47d7b73SSascha Hauer >; 476*c47d7b73SSascha Hauer }; 477*c47d7b73SSascha Hauer}; 478