1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2724ba675SRob Herring/* 3724ba675SRob Herring * Device Tree Source for OMAP34xx/OMAP35xx SoC 4724ba675SRob Herring * 5724ba675SRob Herring * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6724ba675SRob Herring */ 7724ba675SRob Herring 8724ba675SRob Herring#include <dt-bindings/bus/ti-sysc.h> 9724ba675SRob Herring#include <dt-bindings/media/omap3-isp.h> 10724ba675SRob Herring 11724ba675SRob Herring#include "omap3.dtsi" 12724ba675SRob Herring 13724ba675SRob Herring/ { 14724ba675SRob Herring cpus { 15724ba675SRob Herring cpu: cpu@0 { 16724ba675SRob Herring /* OMAP343x/OMAP35xx variants OPP1-6 */ 17724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 18724ba675SRob Herring 19724ba675SRob Herring clock-latency = <300000>; /* From legacy driver */ 20724ba675SRob Herring #cooling-cells = <2>; 21724ba675SRob Herring }; 22724ba675SRob Herring }; 23724ba675SRob Herring 24724ba675SRob Herring cpu0_opp_table: opp-table { 25724ba675SRob Herring compatible = "operating-points-v2-ti-cpu"; 26724ba675SRob Herring syscon = <&scm_conf>; 27724ba675SRob Herring 285821d766SNishanth Menon opp-125000000 { 29724ba675SRob Herring opp-hz = /bits/ 64 <125000000>; 30724ba675SRob Herring /* 31724ba675SRob Herring * we currently only select the max voltage from table 32724ba675SRob Herring * Table 3-3 of the omap3530 Data sheet (SPRS507F). 33724ba675SRob Herring * Format is: <target min max> 34724ba675SRob Herring */ 35724ba675SRob Herring opp-microvolt = <975000 975000 975000>; 36724ba675SRob Herring /* 37724ba675SRob Herring * first value is silicon revision bit mask 38724ba675SRob Herring * second one 720MHz Device Identification bit mask 39724ba675SRob Herring */ 40724ba675SRob Herring opp-supported-hw = <0xffffffff 3>; 41724ba675SRob Herring }; 42724ba675SRob Herring 435821d766SNishanth Menon opp-250000000 { 44724ba675SRob Herring opp-hz = /bits/ 64 <250000000>; 45724ba675SRob Herring opp-microvolt = <1075000 1075000 1075000>; 46724ba675SRob Herring opp-supported-hw = <0xffffffff 3>; 47724ba675SRob Herring opp-suspend; 48724ba675SRob Herring }; 49724ba675SRob Herring 505821d766SNishanth Menon opp-500000000 { 51724ba675SRob Herring opp-hz = /bits/ 64 <500000000>; 52724ba675SRob Herring opp-microvolt = <1200000 1200000 1200000>; 53724ba675SRob Herring opp-supported-hw = <0xffffffff 3>; 54724ba675SRob Herring }; 55724ba675SRob Herring 565821d766SNishanth Menon opp-550000000 { 57724ba675SRob Herring opp-hz = /bits/ 64 <550000000>; 58724ba675SRob Herring opp-microvolt = <1275000 1275000 1275000>; 59724ba675SRob Herring opp-supported-hw = <0xffffffff 3>; 60724ba675SRob Herring }; 61724ba675SRob Herring 625821d766SNishanth Menon opp-600000000 { 63724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 64724ba675SRob Herring opp-microvolt = <1350000 1350000 1350000>; 65724ba675SRob Herring opp-supported-hw = <0xffffffff 3>; 66724ba675SRob Herring }; 67724ba675SRob Herring 685821d766SNishanth Menon opp-720000000 { 69724ba675SRob Herring opp-hz = /bits/ 64 <720000000>; 70724ba675SRob Herring opp-microvolt = <1350000 1350000 1350000>; 71724ba675SRob Herring /* only high-speed grade omap3530 devices */ 72724ba675SRob Herring opp-supported-hw = <0xffffffff 2>; 73724ba675SRob Herring turbo-mode; 74724ba675SRob Herring }; 75724ba675SRob Herring }; 76724ba675SRob Herring 77724ba675SRob Herring ocp@68000000 { 78724ba675SRob Herring omap3_pmx_core2: pinmux@480025d8 { 79724ba675SRob Herring compatible = "ti,omap3-padconf", "pinctrl-single"; 80724ba675SRob Herring reg = <0x480025d8 0x24>; 81724ba675SRob Herring #address-cells = <1>; 82724ba675SRob Herring #size-cells = <0>; 83724ba675SRob Herring #pinctrl-cells = <1>; 84724ba675SRob Herring #interrupt-cells = <1>; 85724ba675SRob Herring interrupt-controller; 86724ba675SRob Herring pinctrl-single,register-width = <16>; 87724ba675SRob Herring pinctrl-single,function-mask = <0xff1f>; 88724ba675SRob Herring }; 89724ba675SRob Herring 90724ba675SRob Herring isp: isp@480bc000 { 91724ba675SRob Herring compatible = "ti,omap3-isp"; 92724ba675SRob Herring reg = <0x480bc000 0x12fc 93724ba675SRob Herring 0x480bd800 0x017c>; 94724ba675SRob Herring interrupts = <24>; 95724ba675SRob Herring iommus = <&mmu_isp>; 96724ba675SRob Herring syscon = <&scm_conf 0x6c>; 97724ba675SRob Herring ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>; 98724ba675SRob Herring #clock-cells = <1>; 99724ba675SRob Herring ports { 100724ba675SRob Herring #address-cells = <1>; 101724ba675SRob Herring #size-cells = <0>; 102724ba675SRob Herring }; 103724ba675SRob Herring }; 104724ba675SRob Herring 105724ba675SRob Herring bandgap: bandgap@48002524 { 106724ba675SRob Herring reg = <0x48002524 0x4>; 107724ba675SRob Herring compatible = "ti,omap34xx-bandgap"; 108724ba675SRob Herring #thermal-sensor-cells = <0>; 109724ba675SRob Herring }; 110724ba675SRob Herring 111724ba675SRob Herring target-module@480cb000 { 112724ba675SRob Herring compatible = "ti,sysc-omap3430-sr", "ti,sysc"; 113724ba675SRob Herring ti,hwmods = "smartreflex_core"; 114724ba675SRob Herring reg = <0x480cb024 0x4>; 115724ba675SRob Herring reg-names = "sysc"; 116724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>; 117724ba675SRob Herring clocks = <&sr2_fck>; 118724ba675SRob Herring clock-names = "fck"; 119724ba675SRob Herring #address-cells = <1>; 120724ba675SRob Herring #size-cells = <1>; 121724ba675SRob Herring ranges = <0 0x480cb000 0x001000>; 122724ba675SRob Herring 123724ba675SRob Herring smartreflex_core: smartreflex@0 { 124724ba675SRob Herring compatible = "ti,omap3-smartreflex-core"; 125724ba675SRob Herring reg = <0 0x400>; 126724ba675SRob Herring interrupts = <19>; 127724ba675SRob Herring }; 128724ba675SRob Herring }; 129724ba675SRob Herring 130724ba675SRob Herring target-module@480c9000 { 131724ba675SRob Herring compatible = "ti,sysc-omap3430-sr", "ti,sysc"; 132724ba675SRob Herring ti,hwmods = "smartreflex_mpu_iva"; 133724ba675SRob Herring reg = <0x480c9024 0x4>; 134724ba675SRob Herring reg-names = "sysc"; 135724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>; 136724ba675SRob Herring clocks = <&sr1_fck>; 137724ba675SRob Herring clock-names = "fck"; 138724ba675SRob Herring #address-cells = <1>; 139724ba675SRob Herring #size-cells = <1>; 140724ba675SRob Herring ranges = <0 0x480c9000 0x001000>; 141724ba675SRob Herring 142724ba675SRob Herring smartreflex_mpu_iva: smartreflex@480c9000 { 143724ba675SRob Herring compatible = "ti,omap3-smartreflex-mpu-iva"; 144724ba675SRob Herring reg = <0 0x400>; 145724ba675SRob Herring interrupts = <18>; 146724ba675SRob Herring }; 147724ba675SRob Herring }; 148724ba675SRob Herring 149724ba675SRob Herring /* 150724ba675SRob Herring * On omap34xx the OCP registers do not seem to be accessible 151724ba675SRob Herring * at all unlike on 36xx. Maybe SGX is permanently set to 152724ba675SRob Herring * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is 153724ba675SRob Herring * write-only at 0x50000e10. We detect SGX based on the SGX 154724ba675SRob Herring * revision register instead of the unreadable OCP revision 155724ba675SRob Herring * register. Also note that on early 34xx es1 revision there 156724ba675SRob Herring * are also different clocks, but we do not have any dts users 157724ba675SRob Herring * for it. 158724ba675SRob Herring */ 159724ba675SRob Herring sgx_module: target-module@50000000 { 160724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 161724ba675SRob Herring reg = <0x50000014 0x4>; 162724ba675SRob Herring reg-names = "rev"; 163724ba675SRob Herring clocks = <&sgx_fck>, <&sgx_ick>; 164724ba675SRob Herring clock-names = "fck", "ick"; 165724ba675SRob Herring #address-cells = <1>; 166724ba675SRob Herring #size-cells = <1>; 167*70f028ffSAndrew Davis ranges = <0 0x50000000 0x10000>; 168724ba675SRob Herring 169*70f028ffSAndrew Davis gpu@0 { 170*70f028ffSAndrew Davis compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; 171*70f028ffSAndrew Davis reg = <0x0 0x10000>; /* 64kB */ 172*70f028ffSAndrew Davis interrupts = <21>; 173*70f028ffSAndrew Davis }; 174724ba675SRob Herring }; 175724ba675SRob Herring }; 176724ba675SRob Herring 177724ba675SRob Herring thermal_zones: thermal-zones { 178724ba675SRob Herring #include "omap3-cpu-thermal.dtsi" 179724ba675SRob Herring }; 180724ba675SRob Herring}; 181724ba675SRob Herring 182724ba675SRob Herring&ssi { 183724ba675SRob Herring status = "okay"; 184724ba675SRob Herring 185724ba675SRob Herring clocks = <&ssi_ssr_fck>, 186724ba675SRob Herring <&ssi_sst_fck>, 187724ba675SRob Herring <&ssi_ick>; 188724ba675SRob Herring clock-names = "ssi_ssr_fck", 189724ba675SRob Herring "ssi_sst_fck", 190724ba675SRob Herring "ssi_ick"; 191724ba675SRob Herring}; 192724ba675SRob Herring 193724ba675SRob Herring&usb_otg_target { 194724ba675SRob Herring clocks = <&hsotgusb_ick_3430es2>; 195724ba675SRob Herring}; 196724ba675SRob Herring 197724ba675SRob Herring/include/ "omap34xx-omap36xx-clocks.dtsi" 198724ba675SRob Herring/include/ "omap36xx-omap3430es2plus-clocks.dtsi" 199724ba675SRob Herring/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 200