157000675SSricharan Ramabadhran// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 257000675SSricharan Ramabadhran/* 357000675SSricharan Ramabadhran * IPQ5018 SoC device tree source 457000675SSricharan Ramabadhran * 557000675SSricharan Ramabadhran * Copyright (c) 2023 The Linux Foundation. All rights reserved. 657000675SSricharan Ramabadhran */ 757000675SSricharan Ramabadhran 83e4b53e0SGokul Sriram Palanisamy#include <dt-bindings/clock/qcom,apss-ipq.h> 957000675SSricharan Ramabadhran#include <dt-bindings/interrupt-controller/arm-gic.h> 1057000675SSricharan Ramabadhran#include <dt-bindings/clock/qcom,gcc-ipq5018.h> 1157000675SSricharan Ramabadhran#include <dt-bindings/reset/qcom,gcc-ipq5018.h> 1257000675SSricharan Ramabadhran 1357000675SSricharan Ramabadhran/ { 1457000675SSricharan Ramabadhran interrupt-parent = <&intc>; 1557000675SSricharan Ramabadhran #address-cells = <2>; 1657000675SSricharan Ramabadhran #size-cells = <2>; 1757000675SSricharan Ramabadhran 1857000675SSricharan Ramabadhran clocks { 1957000675SSricharan Ramabadhran sleep_clk: sleep-clk { 2057000675SSricharan Ramabadhran compatible = "fixed-clock"; 2157000675SSricharan Ramabadhran #clock-cells = <0>; 2257000675SSricharan Ramabadhran }; 2357000675SSricharan Ramabadhran 2457000675SSricharan Ramabadhran xo_board_clk: xo-board-clk { 2557000675SSricharan Ramabadhran compatible = "fixed-clock"; 2657000675SSricharan Ramabadhran #clock-cells = <0>; 2757000675SSricharan Ramabadhran }; 2857000675SSricharan Ramabadhran }; 2957000675SSricharan Ramabadhran 3057000675SSricharan Ramabadhran cpus { 3157000675SSricharan Ramabadhran #address-cells = <1>; 3257000675SSricharan Ramabadhran #size-cells = <0>; 3357000675SSricharan Ramabadhran 3457000675SSricharan Ramabadhran CPU0: cpu@0 { 3557000675SSricharan Ramabadhran device_type = "cpu"; 3657000675SSricharan Ramabadhran compatible = "arm,cortex-a53"; 3757000675SSricharan Ramabadhran reg = <0x0>; 3857000675SSricharan Ramabadhran enable-method = "psci"; 3957000675SSricharan Ramabadhran next-level-cache = <&L2_0>; 403e4b53e0SGokul Sriram Palanisamy clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 413e4b53e0SGokul Sriram Palanisamy operating-points-v2 = <&cpu_opp_table>; 4257000675SSricharan Ramabadhran }; 4357000675SSricharan Ramabadhran 4457000675SSricharan Ramabadhran CPU1: cpu@1 { 4557000675SSricharan Ramabadhran device_type = "cpu"; 4657000675SSricharan Ramabadhran compatible = "arm,cortex-a53"; 4757000675SSricharan Ramabadhran reg = <0x1>; 4857000675SSricharan Ramabadhran enable-method = "psci"; 4957000675SSricharan Ramabadhran next-level-cache = <&L2_0>; 503e4b53e0SGokul Sriram Palanisamy clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 513e4b53e0SGokul Sriram Palanisamy operating-points-v2 = <&cpu_opp_table>; 5257000675SSricharan Ramabadhran }; 5357000675SSricharan Ramabadhran 5457000675SSricharan Ramabadhran L2_0: l2-cache { 5557000675SSricharan Ramabadhran compatible = "cache"; 5657000675SSricharan Ramabadhran cache-level = <2>; 5757000675SSricharan Ramabadhran cache-size = <0x80000>; 5857000675SSricharan Ramabadhran cache-unified; 5957000675SSricharan Ramabadhran }; 6057000675SSricharan Ramabadhran }; 6157000675SSricharan Ramabadhran 623e4b53e0SGokul Sriram Palanisamy cpu_opp_table: opp-table-cpu { 633e4b53e0SGokul Sriram Palanisamy compatible = "operating-points-v2"; 643e4b53e0SGokul Sriram Palanisamy opp-shared; 653e4b53e0SGokul Sriram Palanisamy 663e4b53e0SGokul Sriram Palanisamy opp-800000000 { 673e4b53e0SGokul Sriram Palanisamy opp-hz = /bits/ 64 <800000000>; 683e4b53e0SGokul Sriram Palanisamy opp-microvolt = <1100000>; 693e4b53e0SGokul Sriram Palanisamy clock-latency-ns = <200000>; 703e4b53e0SGokul Sriram Palanisamy }; 713e4b53e0SGokul Sriram Palanisamy 723e4b53e0SGokul Sriram Palanisamy opp-1008000000 { 733e4b53e0SGokul Sriram Palanisamy opp-hz = /bits/ 64 <1008000000>; 743e4b53e0SGokul Sriram Palanisamy opp-microvolt = <1100000>; 753e4b53e0SGokul Sriram Palanisamy clock-latency-ns = <200000>; 763e4b53e0SGokul Sriram Palanisamy }; 773e4b53e0SGokul Sriram Palanisamy }; 783e4b53e0SGokul Sriram Palanisamy 7957000675SSricharan Ramabadhran firmware { 8057000675SSricharan Ramabadhran scm { 8157000675SSricharan Ramabadhran compatible = "qcom,scm-ipq5018", "qcom,scm"; 8279796e87SRobert Marko qcom,sdi-enabled; 8357000675SSricharan Ramabadhran }; 8457000675SSricharan Ramabadhran }; 8557000675SSricharan Ramabadhran 8657000675SSricharan Ramabadhran memory@40000000 { 8757000675SSricharan Ramabadhran device_type = "memory"; 8857000675SSricharan Ramabadhran /* We expect the bootloader to fill in the size */ 8957000675SSricharan Ramabadhran reg = <0x0 0x40000000 0x0 0x0>; 9057000675SSricharan Ramabadhran }; 9157000675SSricharan Ramabadhran 9257000675SSricharan Ramabadhran pmu { 9357000675SSricharan Ramabadhran compatible = "arm,cortex-a53-pmu"; 9457000675SSricharan Ramabadhran interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9557000675SSricharan Ramabadhran }; 9657000675SSricharan Ramabadhran 9757000675SSricharan Ramabadhran psci { 9857000675SSricharan Ramabadhran compatible = "arm,psci-1.0"; 9957000675SSricharan Ramabadhran method = "smc"; 10057000675SSricharan Ramabadhran }; 10157000675SSricharan Ramabadhran 10257000675SSricharan Ramabadhran reserved-memory { 10357000675SSricharan Ramabadhran #address-cells = <2>; 10457000675SSricharan Ramabadhran #size-cells = <2>; 10557000675SSricharan Ramabadhran ranges; 10657000675SSricharan Ramabadhran 107*a427dd16SKathiravan Thirumoorthy bootloader@4a800000 { 108*a427dd16SKathiravan Thirumoorthy reg = <0x0 0x4a800000 0x0 0x200000>; 109*a427dd16SKathiravan Thirumoorthy no-map; 110*a427dd16SKathiravan Thirumoorthy }; 111*a427dd16SKathiravan Thirumoorthy 112*a427dd16SKathiravan Thirumoorthy sbl@4aa00000 { 113*a427dd16SKathiravan Thirumoorthy reg = <0x0 0x4aa00000 0x0 0x100000>; 114*a427dd16SKathiravan Thirumoorthy no-map; 115*a427dd16SKathiravan Thirumoorthy }; 116*a427dd16SKathiravan Thirumoorthy 117*a427dd16SKathiravan Thirumoorthy smem@4ab00000 { 118*a427dd16SKathiravan Thirumoorthy compatible = "qcom,smem"; 119*a427dd16SKathiravan Thirumoorthy reg = <0x0 0x4ab00000 0x0 0x100000>; 120*a427dd16SKathiravan Thirumoorthy no-map; 121*a427dd16SKathiravan Thirumoorthy 122*a427dd16SKathiravan Thirumoorthy hwlocks = <&tcsr_mutex 3>; 123*a427dd16SKathiravan Thirumoorthy }; 124*a427dd16SKathiravan Thirumoorthy 12557000675SSricharan Ramabadhran tz_region: tz@4ac00000 { 12657000675SSricharan Ramabadhran reg = <0x0 0x4ac00000 0x0 0x200000>; 12757000675SSricharan Ramabadhran no-map; 12857000675SSricharan Ramabadhran }; 12957000675SSricharan Ramabadhran }; 13057000675SSricharan Ramabadhran 13157000675SSricharan Ramabadhran soc: soc@0 { 13257000675SSricharan Ramabadhran compatible = "simple-bus"; 13357000675SSricharan Ramabadhran #address-cells = <1>; 13457000675SSricharan Ramabadhran #size-cells = <1>; 13557000675SSricharan Ramabadhran ranges = <0 0 0 0xffffffff>; 13657000675SSricharan Ramabadhran 137e7166f27SNitheesh Sekar usbphy0: phy@5b000 { 138e7166f27SNitheesh Sekar compatible = "qcom,ipq5018-usb-hsphy"; 139e7166f27SNitheesh Sekar reg = <0x0005b000 0x120>; 140e7166f27SNitheesh Sekar 141e7166f27SNitheesh Sekar clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 142e7166f27SNitheesh Sekar 143e7166f27SNitheesh Sekar resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 144e7166f27SNitheesh Sekar 145e7166f27SNitheesh Sekar #phy-cells = <0>; 146e7166f27SNitheesh Sekar 147e7166f27SNitheesh Sekar status = "disabled"; 148e7166f27SNitheesh Sekar }; 149e7166f27SNitheesh Sekar 15057000675SSricharan Ramabadhran tlmm: pinctrl@1000000 { 15157000675SSricharan Ramabadhran compatible = "qcom,ipq5018-tlmm"; 15257000675SSricharan Ramabadhran reg = <0x01000000 0x300000>; 15357000675SSricharan Ramabadhran interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 15457000675SSricharan Ramabadhran gpio-controller; 15557000675SSricharan Ramabadhran #gpio-cells = <2>; 15657000675SSricharan Ramabadhran gpio-ranges = <&tlmm 0 0 47>; 15757000675SSricharan Ramabadhran interrupt-controller; 15857000675SSricharan Ramabadhran #interrupt-cells = <2>; 15957000675SSricharan Ramabadhran 16057000675SSricharan Ramabadhran uart1_pins: uart1-state { 16157000675SSricharan Ramabadhran pins = "gpio31", "gpio32", "gpio33", "gpio34"; 16257000675SSricharan Ramabadhran function = "blsp1_uart1"; 16357000675SSricharan Ramabadhran drive-strength = <8>; 16457000675SSricharan Ramabadhran bias-pull-down; 16557000675SSricharan Ramabadhran }; 16657000675SSricharan Ramabadhran }; 16757000675SSricharan Ramabadhran 16857000675SSricharan Ramabadhran gcc: clock-controller@1800000 { 16957000675SSricharan Ramabadhran compatible = "qcom,gcc-ipq5018"; 17057000675SSricharan Ramabadhran reg = <0x01800000 0x80000>; 17157000675SSricharan Ramabadhran clocks = <&xo_board_clk>, 17257000675SSricharan Ramabadhran <&sleep_clk>, 17357000675SSricharan Ramabadhran <0>, 17457000675SSricharan Ramabadhran <0>, 17557000675SSricharan Ramabadhran <0>, 17657000675SSricharan Ramabadhran <0>, 17757000675SSricharan Ramabadhran <0>, 17857000675SSricharan Ramabadhran <0>, 17957000675SSricharan Ramabadhran <0>; 18057000675SSricharan Ramabadhran #clock-cells = <1>; 18157000675SSricharan Ramabadhran #reset-cells = <1>; 18257000675SSricharan Ramabadhran }; 18357000675SSricharan Ramabadhran 184*a427dd16SKathiravan Thirumoorthy tcsr_mutex: hwlock@1905000 { 185*a427dd16SKathiravan Thirumoorthy compatible = "qcom,tcsr-mutex"; 186*a427dd16SKathiravan Thirumoorthy reg = <0x01905000 0x20000>; 187*a427dd16SKathiravan Thirumoorthy #hwlock-cells = <1>; 188*a427dd16SKathiravan Thirumoorthy }; 189*a427dd16SKathiravan Thirumoorthy 19057000675SSricharan Ramabadhran sdhc_1: mmc@7804000 { 19157000675SSricharan Ramabadhran compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; 19257000675SSricharan Ramabadhran reg = <0x7804000 0x1000>; 19357000675SSricharan Ramabadhran reg-names = "hc"; 19457000675SSricharan Ramabadhran 19557000675SSricharan Ramabadhran interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 19657000675SSricharan Ramabadhran <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 19757000675SSricharan Ramabadhran interrupt-names = "hc_irq", "pwr_irq"; 19857000675SSricharan Ramabadhran 19957000675SSricharan Ramabadhran clocks = <&gcc GCC_SDCC1_AHB_CLK>, 20057000675SSricharan Ramabadhran <&gcc GCC_SDCC1_APPS_CLK>, 20157000675SSricharan Ramabadhran <&xo_board_clk>; 20257000675SSricharan Ramabadhran clock-names = "iface", "core", "xo"; 20357000675SSricharan Ramabadhran non-removable; 20457000675SSricharan Ramabadhran status = "disabled"; 20557000675SSricharan Ramabadhran }; 20657000675SSricharan Ramabadhran 207a1f42e08SRobert Marko blsp_dma: dma-controller@7884000 { 208a1f42e08SRobert Marko compatible = "qcom,bam-v1.7.0"; 209a1f42e08SRobert Marko reg = <0x07884000 0x1d000>; 210a1f42e08SRobert Marko interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 211a1f42e08SRobert Marko clocks = <&gcc GCC_BLSP1_AHB_CLK>; 212a1f42e08SRobert Marko clock-names = "bam_clk"; 213a1f42e08SRobert Marko #dma-cells = <1>; 214a1f42e08SRobert Marko qcom,ee = <0>; 215a1f42e08SRobert Marko }; 216a1f42e08SRobert Marko 21757000675SSricharan Ramabadhran blsp1_uart1: serial@78af000 { 21857000675SSricharan Ramabadhran compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 21957000675SSricharan Ramabadhran reg = <0x078af000 0x200>; 22057000675SSricharan Ramabadhran interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 22157000675SSricharan Ramabadhran clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 22257000675SSricharan Ramabadhran <&gcc GCC_BLSP1_AHB_CLK>; 22357000675SSricharan Ramabadhran clock-names = "core", "iface"; 22457000675SSricharan Ramabadhran status = "disabled"; 22557000675SSricharan Ramabadhran }; 22657000675SSricharan Ramabadhran 227a1f42e08SRobert Marko blsp1_spi1: spi@78b5000 { 228a1f42e08SRobert Marko compatible = "qcom,spi-qup-v2.2.1"; 229a1f42e08SRobert Marko #address-cells = <1>; 230a1f42e08SRobert Marko #size-cells = <0>; 231a1f42e08SRobert Marko reg = <0x078b5000 0x600>; 232a1f42e08SRobert Marko interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 233a1f42e08SRobert Marko clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 234a1f42e08SRobert Marko <&gcc GCC_BLSP1_AHB_CLK>; 235a1f42e08SRobert Marko clock-names = "core", "iface"; 236a1f42e08SRobert Marko dmas = <&blsp_dma 4>, <&blsp_dma 5>; 237a1f42e08SRobert Marko dma-names = "tx", "rx"; 238a1f42e08SRobert Marko status = "disabled"; 239a1f42e08SRobert Marko }; 240a1f42e08SRobert Marko 241e7166f27SNitheesh Sekar usb: usb@8af8800 { 242e7166f27SNitheesh Sekar compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; 243e7166f27SNitheesh Sekar reg = <0x08af8800 0x400>; 244e7166f27SNitheesh Sekar 245e7166f27SNitheesh Sekar interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 246e7166f27SNitheesh Sekar interrupt-names = "hs_phy_irq"; 247e7166f27SNitheesh Sekar 248e7166f27SNitheesh Sekar clocks = <&gcc GCC_USB0_MASTER_CLK>, 249e7166f27SNitheesh Sekar <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 250e7166f27SNitheesh Sekar <&gcc GCC_USB0_SLEEP_CLK>, 251e7166f27SNitheesh Sekar <&gcc GCC_USB0_MOCK_UTMI_CLK>; 252e7166f27SNitheesh Sekar clock-names = "core", 253e7166f27SNitheesh Sekar "iface", 254e7166f27SNitheesh Sekar "sleep", 255e7166f27SNitheesh Sekar "mock_utmi"; 256e7166f27SNitheesh Sekar 257e7166f27SNitheesh Sekar resets = <&gcc GCC_USB0_BCR>; 258e7166f27SNitheesh Sekar 259e7166f27SNitheesh Sekar qcom,select-utmi-as-pipe-clk; 260e7166f27SNitheesh Sekar #address-cells = <1>; 261e7166f27SNitheesh Sekar #size-cells = <1>; 262e7166f27SNitheesh Sekar ranges; 263e7166f27SNitheesh Sekar 264e7166f27SNitheesh Sekar status = "disabled"; 265e7166f27SNitheesh Sekar 266e7166f27SNitheesh Sekar usb_dwc: usb@8a00000 { 267e7166f27SNitheesh Sekar compatible = "snps,dwc3"; 268e7166f27SNitheesh Sekar reg = <0x08a00000 0xe000>; 269e7166f27SNitheesh Sekar clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 270e7166f27SNitheesh Sekar clock-names = "ref"; 271e7166f27SNitheesh Sekar interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 272e7166f27SNitheesh Sekar phy-names = "usb2-phy"; 273e7166f27SNitheesh Sekar phys = <&usbphy0>; 274e7166f27SNitheesh Sekar tx-fifo-resize; 275e7166f27SNitheesh Sekar snps,is-utmi-l1-suspend; 276e7166f27SNitheesh Sekar snps,hird-threshold = /bits/ 8 <0x0>; 277e7166f27SNitheesh Sekar snps,dis_u2_susphy_quirk; 278e7166f27SNitheesh Sekar snps,dis_u3_susphy_quirk; 279e7166f27SNitheesh Sekar }; 280e7166f27SNitheesh Sekar }; 281e7166f27SNitheesh Sekar 28257000675SSricharan Ramabadhran intc: interrupt-controller@b000000 { 28357000675SSricharan Ramabadhran compatible = "qcom,msm-qgic2"; 28457000675SSricharan Ramabadhran reg = <0x0b000000 0x1000>, /* GICD */ 28557000675SSricharan Ramabadhran <0x0b002000 0x2000>, /* GICC */ 28657000675SSricharan Ramabadhran <0x0b001000 0x1000>, /* GICH */ 28757000675SSricharan Ramabadhran <0x0b004000 0x2000>; /* GICV */ 28857000675SSricharan Ramabadhran interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 28957000675SSricharan Ramabadhran interrupt-controller; 29057000675SSricharan Ramabadhran #interrupt-cells = <3>; 29157000675SSricharan Ramabadhran #address-cells = <1>; 29257000675SSricharan Ramabadhran #size-cells = <1>; 29357000675SSricharan Ramabadhran ranges = <0 0x0b00a000 0x1ffa>; 29457000675SSricharan Ramabadhran 29557000675SSricharan Ramabadhran v2m0: v2m@0 { 29657000675SSricharan Ramabadhran compatible = "arm,gic-v2m-frame"; 29757000675SSricharan Ramabadhran reg = <0x00000000 0xff8>; 29857000675SSricharan Ramabadhran msi-controller; 29957000675SSricharan Ramabadhran }; 30057000675SSricharan Ramabadhran 30157000675SSricharan Ramabadhran v2m1: v2m@1000 { 30257000675SSricharan Ramabadhran compatible = "arm,gic-v2m-frame"; 30357000675SSricharan Ramabadhran reg = <0x00001000 0xff8>; 30457000675SSricharan Ramabadhran msi-controller; 30557000675SSricharan Ramabadhran }; 30657000675SSricharan Ramabadhran }; 30757000675SSricharan Ramabadhran 3089cbaee83SRobert Marko watchdog: watchdog@b017000 { 3099cbaee83SRobert Marko compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; 3109cbaee83SRobert Marko reg = <0x0b017000 0x40>; 3119cbaee83SRobert Marko interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 3129cbaee83SRobert Marko clocks = <&sleep_clk>; 3139cbaee83SRobert Marko }; 3149cbaee83SRobert Marko 3153e4b53e0SGokul Sriram Palanisamy apcs_glb: mailbox@b111000 { 3163e4b53e0SGokul Sriram Palanisamy compatible = "qcom,ipq5018-apcs-apps-global", 3173e4b53e0SGokul Sriram Palanisamy "qcom,ipq6018-apcs-apps-global"; 3183e4b53e0SGokul Sriram Palanisamy reg = <0x0b111000 0x1000>; 3193e4b53e0SGokul Sriram Palanisamy #clock-cells = <1>; 3203e4b53e0SGokul Sriram Palanisamy clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; 3213e4b53e0SGokul Sriram Palanisamy clock-names = "pll", "xo", "gpll0"; 3223e4b53e0SGokul Sriram Palanisamy #mbox-cells = <1>; 3233e4b53e0SGokul Sriram Palanisamy }; 3243e4b53e0SGokul Sriram Palanisamy 3253e4b53e0SGokul Sriram Palanisamy a53pll: clock@b116000 { 3263e4b53e0SGokul Sriram Palanisamy compatible = "qcom,ipq5018-a53pll"; 3273e4b53e0SGokul Sriram Palanisamy reg = <0x0b116000 0x40>; 3283e4b53e0SGokul Sriram Palanisamy #clock-cells = <0>; 3293e4b53e0SGokul Sriram Palanisamy clocks = <&xo_board_clk>; 3303e4b53e0SGokul Sriram Palanisamy clock-names = "xo"; 3313e4b53e0SGokul Sriram Palanisamy }; 3323e4b53e0SGokul Sriram Palanisamy 33357000675SSricharan Ramabadhran timer@b120000 { 33457000675SSricharan Ramabadhran compatible = "arm,armv7-timer-mem"; 33557000675SSricharan Ramabadhran reg = <0x0b120000 0x1000>; 33657000675SSricharan Ramabadhran #address-cells = <1>; 33757000675SSricharan Ramabadhran #size-cells = <1>; 33857000675SSricharan Ramabadhran ranges; 33957000675SSricharan Ramabadhran 34057000675SSricharan Ramabadhran frame@b120000 { 34157000675SSricharan Ramabadhran reg = <0x0b121000 0x1000>, 34257000675SSricharan Ramabadhran <0x0b122000 0x1000>; 34357000675SSricharan Ramabadhran interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 34457000675SSricharan Ramabadhran <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 34557000675SSricharan Ramabadhran frame-number = <0>; 34657000675SSricharan Ramabadhran }; 34757000675SSricharan Ramabadhran 34857000675SSricharan Ramabadhran frame@b123000 { 34957000675SSricharan Ramabadhran reg = <0xb123000 0x1000>; 35057000675SSricharan Ramabadhran interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 35157000675SSricharan Ramabadhran frame-number = <1>; 35257000675SSricharan Ramabadhran status = "disabled"; 35357000675SSricharan Ramabadhran }; 35457000675SSricharan Ramabadhran 35557000675SSricharan Ramabadhran frame@b124000 { 35657000675SSricharan Ramabadhran frame-number = <2>; 35757000675SSricharan Ramabadhran interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 35857000675SSricharan Ramabadhran reg = <0x0b124000 0x1000>; 35957000675SSricharan Ramabadhran status = "disabled"; 36057000675SSricharan Ramabadhran }; 36157000675SSricharan Ramabadhran 36257000675SSricharan Ramabadhran frame@b125000 { 36357000675SSricharan Ramabadhran reg = <0x0b125000 0x1000>; 36457000675SSricharan Ramabadhran interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 36557000675SSricharan Ramabadhran frame-number = <3>; 36657000675SSricharan Ramabadhran status = "disabled"; 36757000675SSricharan Ramabadhran }; 36857000675SSricharan Ramabadhran 36957000675SSricharan Ramabadhran frame@b126000 { 37057000675SSricharan Ramabadhran reg = <0x0b126000 0x1000>; 37157000675SSricharan Ramabadhran interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 37257000675SSricharan Ramabadhran frame-number = <4>; 37357000675SSricharan Ramabadhran status = "disabled"; 37457000675SSricharan Ramabadhran }; 37557000675SSricharan Ramabadhran 37657000675SSricharan Ramabadhran frame@b127000 { 37757000675SSricharan Ramabadhran reg = <0x0b127000 0x1000>; 37857000675SSricharan Ramabadhran interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 37957000675SSricharan Ramabadhran frame-number = <5>; 38057000675SSricharan Ramabadhran status = "disabled"; 38157000675SSricharan Ramabadhran }; 38257000675SSricharan Ramabadhran 38357000675SSricharan Ramabadhran frame@b128000 { 38457000675SSricharan Ramabadhran reg = <0x0b128000 0x1000>; 38557000675SSricharan Ramabadhran interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 38657000675SSricharan Ramabadhran frame-number = <6>; 38757000675SSricharan Ramabadhran status = "disabled"; 38857000675SSricharan Ramabadhran }; 38957000675SSricharan Ramabadhran }; 39057000675SSricharan Ramabadhran }; 39157000675SSricharan Ramabadhran 39257000675SSricharan Ramabadhran timer { 39357000675SSricharan Ramabadhran compatible = "arm,armv8-timer"; 39457000675SSricharan Ramabadhran interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39557000675SSricharan Ramabadhran <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39657000675SSricharan Ramabadhran <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39757000675SSricharan Ramabadhran <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 39857000675SSricharan Ramabadhran }; 39957000675SSricharan Ramabadhran}; 400