Lines Matching +full:opp +full:- +full:microvolt +full:- +full:speed
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <880000>;
24 clock-latency-ns = <500000>;
26 opp-800000000 {
27 opp-hz = /bits/ 64 <800000000>;
28 opp-microvolt = <880000>;
29 clock-latency-ns = <500000>;
31 opp-1000000000 {
32 opp-hz = /bits/ 64 <1000000000>;
33 opp-microvolt = <880000>;
34 clock-latency-ns = <500000>;
36 opp-1200000000 {
37 opp-hz = /bits/ 64 <1200000000>;
38 opp-microvolt = <880000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
44 cluster23_opp: opp-table-1 {
45 compatible = "operating-points-v2";
46 opp-shared;
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <880000>;
51 clock-latency-ns = <500000>;
53 opp-800000000 {
54 opp-hz = /bits/ 64 <800000000>;
55 opp-microvolt = <880000>;
56 clock-latency-ns = <500000>;
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <880000>;
61 clock-latency-ns = <500000>;
63 opp-1200000000 {
64 opp-hz = /bits/ 64 <1200000000>;
65 opp-microvolt = <880000>;
66 clock-latency-ns = <500000>;
67 opp-suspend;
72 #address-cells = <1>;
73 #size-cells = <0>;
75 cpu-map {
114 compatible = "arm,cortex-a55";
117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
122 operating-points-v2 = <&cluster01_opp>;
126 compatible = "arm,cortex-a55";
129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
134 operating-points-v2 = <&cluster01_opp>;
138 compatible = "arm,cortex-a55";
141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci";
144 cpu-idle-states = <&CPU_SLEEP_0>;
146 operating-points-v2 = <&cluster01_opp>;
150 compatible = "arm,cortex-a55";
153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
158 operating-points-v2 = <&cluster01_opp>;
162 compatible = "arm,cortex-a55";
165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_SLEEP_0>;
170 operating-points-v2 = <&cluster23_opp>;
174 compatible = "arm,cortex-a55";
177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0>;
182 operating-points-v2 = <&cluster23_opp>;
186 compatible = "arm,cortex-a55";
189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_SLEEP_0>;
194 operating-points-v2 = <&cluster23_opp>;
198 compatible = "arm,cortex-a55";
201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci";
204 cpu-idle-states = <&CPU_SLEEP_0>;
206 operating-points-v2 = <&cluster23_opp>;
209 L3_CA55_0: cache-controller-0 {
211 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified;
213 cache-level = <3>;
216 L3_CA55_1: cache-controller-1 {
218 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified;
220 cache-level = <3>;
223 L3_CA55_2: cache-controller-2 {
225 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified;
227 cache-level = <3>;
230 L3_CA55_3: cache-controller-3 {
232 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified;
234 cache-level = <3>;
237 idle-states {
238 entry-method = "psci";
240 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = "arm,idle-state";
242 arm,psci-suspend-param = <0x0010000>;
243 local-timer-stop;
244 entry-latency-us = <400>;
245 exit-latency-us = <500>;
246 min-residency-us = <4000>;
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
255 clock-frequency = <0>;
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
262 clock-frequency = <0>;
265 pcie0_clkref: pcie0-clkref {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
269 clock-frequency = <0>;
272 pcie1_clkref: pcie1-clkref {
273 compatible = "fixed-clock";
274 #clock-cells = <0>;
276 clock-frequency = <0>;
280 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
285 compatible = "arm,psci-1.0", "arm,psci-0.2";
289 /* External SCIF clock - to be overridden by boards that provide it */
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
297 compatible = "simple-bus";
298 interrupt-parent = <&gic>;
299 #address-cells = <2>;
300 #size-cells = <2>;
304 compatible = "renesas,r8a779f0-wdt",
305 "renesas,rcar-gen4-wdt";
309 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
315 compatible = "renesas,pfc-r8a779f0";
321 compatible = "renesas,gpio-r8a779f0",
322 "renesas,rcar-gen4-gpio";
326 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
336 compatible = "renesas,gpio-r8a779f0",
337 "renesas,rcar-gen4-gpio";
341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
351 compatible = "renesas,gpio-r8a779f0",
352 "renesas,rcar-gen4-gpio";
356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
366 compatible = "renesas,gpio-r8a779f0",
367 "renesas,rcar-gen4-gpio";
371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
381 compatible = "renesas,r8a779f0-cmt0",
382 "renesas,rcar-gen4-cmt0";
387 clock-names = "fck";
388 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
394 compatible = "renesas,r8a779f0-cmt1",
395 "renesas,rcar-gen4-cmt1";
406 clock-names = "fck";
407 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
413 compatible = "renesas,r8a779f0-cmt1",
414 "renesas,rcar-gen4-cmt1";
425 clock-names = "fck";
426 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
432 compatible = "renesas,r8a779f0-cmt1",
433 "renesas,rcar-gen4-cmt1";
444 clock-names = "fck";
445 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
450 cpg: clock-controller@e6150000 {
451 compatible = "renesas,r8a779f0-cpg-mssr";
454 clock-names = "extal", "extalr";
455 #clock-cells = <2>;
456 #power-domain-cells = <0>;
457 #reset-cells = <1>;
460 rst: reset-controller@e6160000 {
461 compatible = "renesas,r8a779f0-rst";
465 sysc: system-controller@e6180000 {
466 compatible = "renesas,r8a779f0-sysc";
468 #power-domain-cells = <1>;
472 compatible = "renesas,r8a779f0-thermal";
478 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
480 #thermal-sensor-cells = <1>;
483 intc_ex: interrupt-controller@e61c0000 {
484 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
485 #interrupt-cells = <2>;
486 interrupt-controller;
495 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
499 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
504 interrupt-names = "tuni0", "tuni1", "tuni2";
506 clock-names = "fck";
507 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
513 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
519 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
521 clock-names = "fck";
522 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
528 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
534 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
536 clock-names = "fck";
537 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
543 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
549 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
551 clock-names = "fck";
552 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
558 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
564 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
566 clock-names = "fck";
567 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
573 compatible = "renesas,r8a779f0-ether-serdes";
576 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
578 #phy-cells = <1>;
583 compatible = "renesas,i2c-r8a779f0",
584 "renesas,rcar-gen4-i2c";
588 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
592 dma-names = "tx", "rx", "tx", "rx";
593 i2c-scl-internal-delay-ns = <110>;
594 #address-cells = <1>;
595 #size-cells = <0>;
600 compatible = "renesas,i2c-r8a779f0",
601 "renesas,rcar-gen4-i2c";
605 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
609 dma-names = "tx", "rx", "tx", "rx";
610 i2c-scl-internal-delay-ns = <110>;
611 #address-cells = <1>;
612 #size-cells = <0>;
617 compatible = "renesas,i2c-r8a779f0",
618 "renesas,rcar-gen4-i2c";
622 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
626 dma-names = "tx", "rx", "tx", "rx";
627 i2c-scl-internal-delay-ns = <110>;
628 #address-cells = <1>;
629 #size-cells = <0>;
634 compatible = "renesas,i2c-r8a779f0",
635 "renesas,rcar-gen4-i2c";
639 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
643 dma-names = "tx", "rx", "tx", "rx";
644 i2c-scl-internal-delay-ns = <110>;
645 #address-cells = <1>;
646 #size-cells = <0>;
651 compatible = "renesas,i2c-r8a779f0",
652 "renesas,rcar-gen4-i2c";
656 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
660 dma-names = "tx", "rx", "tx", "rx";
661 i2c-scl-internal-delay-ns = <110>;
662 #address-cells = <1>;
663 #size-cells = <0>;
668 compatible = "renesas,i2c-r8a779f0",
669 "renesas,rcar-gen4-i2c";
673 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
677 dma-names = "tx", "rx", "tx", "rx";
678 i2c-scl-internal-delay-ns = <110>;
679 #address-cells = <1>;
680 #size-cells = <0>;
685 compatible = "renesas,hscif-r8a779f0",
686 "renesas,rcar-gen4-hscif", "renesas,hscif";
692 clock-names = "fck", "brg_int", "scif_clk";
695 dma-names = "tx", "rx", "tx", "rx";
696 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
702 compatible = "renesas,hscif-r8a779f0",
703 "renesas,rcar-gen4-hscif", "renesas,hscif";
709 clock-names = "fck", "brg_int", "scif_clk";
712 dma-names = "tx", "rx", "tx", "rx";
713 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
719 compatible = "renesas,hscif-r8a779f0",
720 "renesas,rcar-gen4-hscif", "renesas,hscif";
726 clock-names = "fck", "brg_int", "scif_clk";
729 dma-names = "tx", "rx", "tx", "rx";
730 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
736 compatible = "renesas,hscif-r8a779f0",
737 "renesas,rcar-gen4-hscif", "renesas,hscif";
743 clock-names = "fck", "brg_int", "scif_clk";
746 dma-names = "tx", "rx", "tx", "rx";
747 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
753 compatible = "renesas,r8a779f0-pcie",
754 "renesas,rcar-gen4-pcie";
759 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
764 interrupt-names = "msi", "dma", "sft_ce", "app";
766 clock-names = "core", "ref";
767 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
769 reset-names = "pwr";
770 max-link-speed = <4>;
771 num-lanes = <2>;
772 #address-cells = <3>;
773 #size-cells = <2>;
774 bus-range = <0x00 0xff>;
778 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
779 #interrupt-cells = <1>;
780 interrupt-map-mask = <0 0 0 7>;
781 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
785 snps,enable-cdm-check;
790 compatible = "renesas,r8a779f0-pcie",
791 "renesas,rcar-gen4-pcie";
796 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
801 interrupt-names = "msi", "dma", "sft_ce", "app";
803 clock-names = "core", "ref";
804 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
806 reset-names = "pwr";
807 max-link-speed = <4>;
808 num-lanes = <2>;
809 #address-cells = <3>;
810 #size-cells = <2>;
811 bus-range = <0x00 0xff>;
815 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
816 #interrupt-cells = <1>;
817 interrupt-map-mask = <0 0 0 7>;
818 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
822 snps,enable-cdm-check;
826 pciec0_ep: pcie-ep@e65d0000 {
827 compatible = "renesas,r8a779f0-pcie-ep",
828 "renesas,rcar-gen4-pcie-ep";
833 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
837 interrupt-names = "dma", "sft_ce", "app";
839 clock-names = "core", "ref";
840 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
842 reset-names = "pwr";
843 max-link-speed = <4>;
844 num-lanes = <2>;
845 max-functions = /bits/ 8 <2>;
849 pciec1_ep: pcie-ep@e65d8000 {
850 compatible = "renesas,r8a779f0-pcie-ep",
851 "renesas,rcar-gen4-pcie-ep";
856 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
860 interrupt-names = "dma", "sft_ce", "app";
862 clock-names = "core", "ref";
863 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
865 reset-names = "pwr";
866 max-link-speed = <4>;
867 num-lanes = <2>;
868 max-functions = /bits/ 8 <2>;
873 compatible = "renesas,r8a779f0-ufs";
877 clock-names = "fck", "ref_clk";
878 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
879 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
885 compatible = "renesas,r8a779f0-ether-switch";
887 reg-names = "base", "secure_base";
935 interrupt-names = "mfwd_error", "race_error",
961 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
965 ethernet-ports {
966 #address-cells = <1>;
967 #size-cells = <0>;
985 compatible = "renesas,scif-r8a779f0",
986 "renesas,rcar-gen4-scif", "renesas,scif";
992 clock-names = "fck", "brg_int", "scif_clk";
995 dma-names = "tx", "rx", "tx", "rx";
996 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1002 compatible = "renesas,scif-r8a779f0",
1003 "renesas,rcar-gen4-scif", "renesas,scif";
1009 clock-names = "fck", "brg_int", "scif_clk";
1012 dma-names = "tx", "rx", "tx", "rx";
1013 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1019 compatible = "renesas,scif-r8a779f0",
1020 "renesas,rcar-gen4-scif", "renesas,scif";
1026 clock-names = "fck", "brg_int", "scif_clk";
1029 dma-names = "tx", "rx", "tx", "rx";
1030 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1036 compatible = "renesas,scif-r8a779f0",
1037 "renesas,rcar-gen4-scif", "renesas,scif";
1043 clock-names = "fck", "brg_int", "scif_clk";
1046 dma-names = "tx", "rx", "tx", "rx";
1047 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1053 compatible = "renesas,msiof-r8a779f0",
1054 "renesas,rcar-gen4-msiof";
1060 dma-names = "tx", "rx", "tx", "rx";
1061 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1069 compatible = "renesas,msiof-r8a779f0",
1070 "renesas,rcar-gen4-msiof";
1076 dma-names = "tx", "rx", "tx", "rx";
1077 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "renesas,msiof-r8a779f0",
1086 "renesas,rcar-gen4-msiof";
1092 dma-names = "tx", "rx", "tx", "rx";
1093 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1101 compatible = "renesas,msiof-r8a779f0",
1102 "renesas,rcar-gen4-msiof";
1108 dma-names = "tx", "rx", "tx", "rx";
1109 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1116 dmac0: dma-controller@e7350000 {
1117 compatible = "renesas,dmac-r8a779f0",
1118 "renesas,rcar-gen4-dmac";
1138 interrupt-names = "error",
1144 clock-names = "fck";
1145 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1147 #dma-cells = <1>;
1148 dma-channels = <16>;
1159 dmac1: dma-controller@e7351000 {
1160 compatible = "renesas,dmac-r8a779f0",
1161 "renesas,rcar-gen4-dmac";
1181 interrupt-names = "error",
1187 clock-names = "fck";
1188 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1190 #dma-cells = <1>;
1191 dma-channels = <16>;
1203 compatible = "renesas,sdhi-r8a779f0",
1204 "renesas,rcar-gen4-sdhi";
1208 clock-names = "core", "clkh";
1209 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1211 max-frequency = <200000000>;
1217 compatible = "renesas,ipmmu-r8a779f0",
1218 "renesas,rcar-gen4-ipmmu-vmsa";
1220 renesas,ipmmu-main = <&ipmmu_mm>;
1221 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222 #iommu-cells = <1>;
1226 compatible = "renesas,ipmmu-r8a779f0",
1227 "renesas,rcar-gen4-ipmmu-vmsa";
1229 renesas,ipmmu-main = <&ipmmu_mm>;
1230 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231 #iommu-cells = <1>;
1235 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas,rcar-gen4-ipmmu-vmsa";
1238 renesas,ipmmu-main = <&ipmmu_mm>;
1239 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>;
1244 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas,rcar-gen4-ipmmu-vmsa";
1247 renesas,ipmmu-main = <&ipmmu_mm>;
1248 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1249 #iommu-cells = <1>;
1253 compatible = "renesas,ipmmu-r8a779f0",
1254 "renesas,rcar-gen4-ipmmu-vmsa";
1258 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1259 #iommu-cells = <1>;
1262 gic: interrupt-controller@f1000000 {
1263 compatible = "arm,gic-v3";
1264 #interrupt-cells = <3>;
1265 #address-cells = <0>;
1266 interrupt-controller;
1278 thermal-zones {
1279 sensor_thermal_rtcore: sensor1-thermal {
1280 polling-delay-passive = <250>;
1281 polling-delay = <1000>;
1282 thermal-sensors = <&tsc 0>;
1285 sensor1_crit: sensor1-crit {
1293 sensor_thermal_apcore0: sensor2-thermal {
1294 polling-delay-passive = <250>;
1295 polling-delay = <1000>;
1296 thermal-sensors = <&tsc 1>;
1299 sensor2_crit: sensor2-crit {
1307 sensor_thermal_apcore4: sensor3-thermal {
1308 polling-delay-passive = <250>;
1309 polling-delay = <1000>;
1310 thermal-sensors = <&tsc 2>;
1313 sensor3_crit: sensor3-crit {
1323 compatible = "arm,armv8-timer";
1324 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1329 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1330 "hyp-virt";
1333 ufs30_clk: ufs30-clk {
1334 compatible = "fixed-clock";
1335 #clock-cells = <0>;
1337 clock-frequency = <0>;