Home
last modified time | relevance | path

Searched +full:de +full:- +full:assertion (Results 1 – 25 of 59) sorted by relevance

123

/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
[all …]
/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
[all …]
/linux/drivers/spi/
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
71 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
72 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
[all …]
/linux/Documentation/translations/sp_SP/process/
H A Dkernel-enforcement-statement.rst1 .. include:: ../disclaimer-sp.rst
3 :Original: :ref:`Documentation/process/kernel-enforcement-statement.rst <process_statement_kernel>`
8 Aplicación de la licencia en el kernel Linux
12 se utiliza nuestro software y cómo se aplica la licencia de nuestro software.
13 El cumplimiento de las obligaciones de intercambio recíproco de GPL-2.0 son
14 fundamentales en el largo plazo para la sostenibilidad de nuestro software
17 Aunque existe el derecho de hacer valer un copyright distinto en las
18 contribuciones hechas a nuestra comunidad, compartimos el interés de
20 de una manera que beneficia a nuestra comunidad y no tenga un indeseado
21 impacto negativo en la salud y crecimiento de nuestro ecosistema de software.
[all …]
/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
75 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
[all …]
/linux/Documentation/scsi/
H A Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
/linux/Documentation/process/
H A Dkernel-enforcement-statement.rst4 ----------------------------------
8 reciprocal sharing obligations of GPL-2.0 is critical to the long-term
20 Notwithstanding the termination provisions of the GPL-2.0, we agree that
22 following provisions of GPL-3.0 as additional permissions under our
23 license with respect to any non-defensive assertion of rights under the
48 Finally, once a non-compliance issue is resolved, we hope the user will feel
55 - Laura Abbott
56 - Bjorn Andersson (Linaro)
57 - Andrea Arcangeli
58 - Neil Armstrong
[all …]
/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
H A Drtc-ti-k3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
46 #define K3RTC_MIN_OFFSET (-277761)
50 .name = "peripheral-registers",
107 * struct ti_k3_rtc - Private data for ti-k3-rtc
129 ret = regmap_field_read(priv->r_fields[f], &val); in k3rtc_field_read()
141 regmap_field_write(priv->r_fields[f], val); in k3rtc_field_write()
145 * k3rtc_fence - Ensure a register sync took place between the two domains
148 * Return: 0 if the sync took place, else returns -ETIMEDOUT
154 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret, in k3rtc_fence()
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
183 /* PCIe Port Logic registers (memory-mapped) */
196 /* PHY registers (not memory-mapped) */
233 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
234 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
[all …]
/linux/drivers/pcmcia/
H A Dpxa2xx_base.c1 // SPDX-License-Identifier: GPL-2.0-only
9 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
31 #include <asm/mach-types.h>
89 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1; in pxa2xx_mcxx_hold()
103 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1; in pxa2xx_mcxx_setup()
106 /* This function returns the (approximate) command assertion period, in
161 unsigned long clk = clk_get_rate(skt->clk) / 10000; in pxa2xx_pcmcia_set_timing()
163 int sock = skt->nr; in pxa2xx_pcmcia_set_timing()
184 if (freqs->new > freqs->old) { in pxa2xx_pcmcia_frequency_change()
186 "pre-updating\n", in pxa2xx_pcmcia_frequency_change()
[all …]
/linux/include/net/caif/
H A Dcaif_layer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson AB 2010
19 * caif_assert() - Assert function for CAIF.
23 * assertion fails. Normally this will do a stack up at the current location.
34 * enum caif_ctrlcmd - CAIF Stack Control Signaling sent in layer.ctrlcmd().
48 * @CAIF_CTRLCMD_DEINIT_RSP: Called when de-initialization is
77 * enum caif_modemcmd - Modem Control Signaling, sent from CAIF Client
102 * enum caif_direction - CAIF Packet Direction.
113 * struct cflayer - CAIF Stack layer.
135 * - All layers must use this structure. If embedding it, then place this
[all …]
/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2012 Anatolij Gustschin <agust@denx.de>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm33xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
20 #include "cm-regbits-34xx.h"
21 #include "cm-regbits-33xx.h"
57 /* Read-modify-write a register in CM */
82 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
98 * _is_module_ready - can module registers be accessed without causing an abort?
116 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
121 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
137 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
[all …]
H A Dcminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2008-2011 Texas Instruments, Inc.
26 #include "cm-regbits-34xx.h"
30 #include "prcm-common.h"
58 * omap_cm_base_init - Populates the cm partitions
77 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
94 * _is_module_ready - can module registers be accessed without causing an abort?
130 /* Read-modify-write a register in CM1. Caller must lock */
171 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
177 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
[all …]
/linux/drivers/net/wireless/ti/wl1251/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
70 * bits 0 - 15: Reserved.
71 * bits 16 - 23: Version ID - The WiLink version ID
73 * bits 24 - 31: Chip ID - The WiLink chip ID.
93 /* 0 - Always active*/
94 /* 1 - Power down mode: light / fast sleep*/
95 /* 2 - ELP mode: Deep / Max sleep*/
191 * 13 Copy RX Status - when set, write three receive status words
195 * 11 RX Complete upon FCS error - when set, give rx complete
[all …]
/linux/Documentation/hid/
H A Dintel-thc-hid.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
37 | +-----------------------------------+ |
39 | +-----------------------------------+ |
40 | +-----------------------------------+ |
[all …]
/linux/drivers/gpio/
H A Dgpio-max3191x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-max3191x.c - GPIO driver for Maxim MAX3191x industrial serializer
8 * Multiple chips can be daisy-chained, the spec does not impose
11 * Either of two modes is selectable: In 8-bit mode, only the state
13 * In 16-bit mode, an additional status byte is clocked out with
17 * readout of non-faulting chips in the same daisy-chain.
21 * daisy-chain.
23 * If the chips are hardwired to 8-bit mode ("modesel" pulled high),
24 * gpio-pisosr.c can be used alternatively to this driver.
30 * https://datasheets.maximintegrated.com/en/ds/MAX31953-MAX31963.pdf
[all …]
/linux/Documentation/hwmon/
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
[all …]
/linux/drivers/usb/musb/
H A Dtusb6010.c1 // SPDX-License-Identifier: GPL-2.0
9 * - Driver assumes that interface to external host (main CPU) is
27 #include <linux/dma-mapping.h>
51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
71 rev = musb->tusb_revision; in tusb_print_revision()
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
123 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-regmap.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
30 struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx; in mcp251xfd_regmap_nocrc_gather_write()
34 .len = sizeof(buf_tx->cmd) + val_len, in mcp251xfd_regmap_nocrc_gather_write()
38 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16)); in mcp251xfd_regmap_nocrc_gather_write()
41 reg_len != sizeof(buf_tx->cmd.cmd)) in mcp251xfd_regmap_nocrc_gather_write()
42 return -EINVAL; in mcp251xfd_regmap_nocrc_gather_write()
44 memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd)); in mcp251xfd_regmap_nocrc_gather_write()
45 memcpy(buf_tx->data, val, val_len); in mcp251xfd_regmap_nocrc_gather_write()
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_int.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
12 #include <linux/dma-mapping.h>
92 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); in qed_mcp_attn_cb()
95 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", in qed_mcp_attn_cb()
97 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, in qed_mcp_attn_cb()
118 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
124 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
126 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
[all …]

123