Lines Matching +full:de +full:- +full:assertion
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
71 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
72 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
77 debugfs_remove_recursive(dws->debugfs); in dw_spi_debugfs_remove()
92 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_set_cs()
93 bool cs_high = !!(spi->mode & SPI_CS_HIGH); in dw_spi_set_cs()
100 * support active-high or active-low CS level. in dw_spi_set_cs()
114 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); in dw_spi_tx_max()
118 * though to use (dws->fifo_len - rxflr - txflr) as in dw_spi_tx_max()
124 rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len); in dw_spi_tx_max()
126 return min3((u32)dws->tx_len, tx_room, rxtx_gap); in dw_spi_tx_max()
132 return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR)); in dw_spi_rx_max()
140 while (max--) { in dw_writer()
141 if (dws->tx) { in dw_writer()
142 if (dws->n_bytes == 1) in dw_writer()
143 txw = *(u8 *)(dws->tx); in dw_writer()
144 else if (dws->n_bytes == 2) in dw_writer()
145 txw = *(u16 *)(dws->tx); in dw_writer()
147 txw = *(u32 *)(dws->tx); in dw_writer()
149 dws->tx += dws->n_bytes; in dw_writer()
152 --dws->tx_len; in dw_writer()
161 while (max--) { in dw_reader()
163 if (dws->rx) { in dw_reader()
164 if (dws->n_bytes == 1) in dw_reader()
165 *(u8 *)(dws->rx) = rxw; in dw_reader()
166 else if (dws->n_bytes == 2) in dw_reader()
167 *(u16 *)(dws->rx) = rxw; in dw_reader()
169 *(u32 *)(dws->rx) = rxw; in dw_reader()
171 dws->rx += dws->n_bytes; in dw_reader()
173 --dws->rx_len; in dw_reader()
188 dev_err(&dws->host->dev, "RX FIFO overflow detected\n"); in dw_spi_check_status()
189 ret = -EIO; in dw_spi_check_status()
193 dev_err(&dws->host->dev, "RX FIFO underflow detected\n"); in dw_spi_check_status()
194 ret = -EIO; in dw_spi_check_status()
198 dev_err(&dws->host->dev, "TX FIFO overflow detected\n"); in dw_spi_check_status()
199 ret = -EIO; in dw_spi_check_status()
205 if (dws->host->cur_msg) in dw_spi_check_status()
206 dws->host->cur_msg->status = ret; in dw_spi_check_status()
218 spi_finalize_current_transfer(dws->host); in dw_spi_transfer_handler()
230 if (!dws->rx_len) { in dw_spi_transfer_handler()
232 spi_finalize_current_transfer(dws->host); in dw_spi_transfer_handler()
233 } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) { in dw_spi_transfer_handler()
234 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1); in dw_spi_transfer_handler()
244 if (!dws->tx_len) in dw_spi_transfer_handler()
260 if (!host->cur_msg) { in dw_spi_irq()
265 return dws->transfer_handler(dws); in dw_spi_irq()
281 if (spi->mode & SPI_CPOL) in dw_spi_prepare_cr0()
283 if (spi->mode & SPI_CPHA) in dw_spi_prepare_cr0()
287 if (spi->mode & SPI_LOOP) in dw_spi_prepare_cr0()
298 if (spi->mode & SPI_CPOL) in dw_spi_prepare_cr0()
300 if (spi->mode & SPI_CPHA) in dw_spi_prepare_cr0()
304 if (spi->mode & SPI_LOOP) in dw_spi_prepare_cr0()
319 u32 cr0 = chip->cr0; in dw_spi_update_config()
324 cr0 |= (cfg->dfs - 1) << dws->dfs_offset; in dw_spi_update_config()
328 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
331 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
335 if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || in dw_spi_update_config()
336 cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) in dw_spi_update_config()
337 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); in dw_spi_update_config()
340 clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe; in dw_spi_update_config()
341 speed_hz = dws->max_freq / clk_div; in dw_spi_update_config()
343 if (dws->current_freq != speed_hz) { in dw_spi_update_config()
345 dws->current_freq = speed_hz; in dw_spi_update_config()
349 if (dws->cur_rx_sample_dly != chip->rx_sample_dly) { in dw_spi_update_config()
350 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly); in dw_spi_update_config()
351 dws->cur_rx_sample_dly = chip->rx_sample_dly; in dw_spi_update_config()
363 * will be adjusted at the final stage of the IRQ-based SPI transfer in dw_spi_irq_setup()
366 level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len); in dw_spi_irq_setup()
368 dw_writel(dws, DW_SPI_RXFTLR, level - 1); in dw_spi_irq_setup()
370 dws->transfer_handler = dw_spi_transfer_handler; in dw_spi_irq_setup()
378 * The iterative procedure of the poll-based transfer is simple: write as much
383 * Note this method the same way as the IRQ-based transfer won't work well for
385 * automatic CS assertion/de-assertion.
395 nbits = dws->n_bytes * BITS_PER_BYTE; in dw_spi_poll_transfer()
400 delay.value = nbits * (dws->rx_len - dws->tx_len); in dw_spi_poll_transfer()
408 } while (dws->rx_len); in dw_spi_poll_transfer()
420 .dfs = transfer->bits_per_word, in dw_spi_transfer_one()
421 .freq = transfer->speed_hz, in dw_spi_transfer_one()
425 dws->dma_mapped = 0; in dw_spi_transfer_one()
426 dws->n_bytes = roundup_pow_of_two(BITS_TO_BYTES(transfer->bits_per_word)); in dw_spi_transfer_one()
427 dws->tx = (void *)transfer->tx_buf; in dw_spi_transfer_one()
428 dws->tx_len = transfer->len / dws->n_bytes; in dw_spi_transfer_one()
429 dws->rx = transfer->rx_buf; in dw_spi_transfer_one()
430 dws->rx_len = dws->tx_len; in dw_spi_transfer_one()
439 transfer->effective_speed_hz = dws->current_freq; in dw_spi_transfer_one()
442 dws->dma_mapped = spi_xfer_is_dma_mapped(host, spi, transfer); in dw_spi_transfer_one()
447 if (dws->dma_mapped) { in dw_spi_transfer_one()
448 ret = dws->dma_ops->dma_setup(dws, transfer); in dw_spi_transfer_one()
455 if (dws->dma_mapped) in dw_spi_transfer_one()
456 return dws->dma_ops->dma_transfer(dws, transfer); in dw_spi_transfer_one()
457 else if (dws->irq == IRQ_NOTCONNECTED) in dw_spi_transfer_one()
470 if (dws->dma_mapped) in dw_spi_handle_err()
471 dws->dma_ops->dma_stop(dws); in dw_spi_handle_err()
478 if (op->data.dir == SPI_MEM_DATA_IN) in dw_spi_adjust_mem_op_size()
479 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1); in dw_spi_adjust_mem_op_size()
487 if (op->data.buswidth > 1 || op->addr.buswidth > 1 || in dw_spi_supports_mem_op()
488 op->dummy.buswidth > 1 || op->cmd.buswidth > 1) in dw_spi_supports_mem_op()
501 * either use the pre-allocated buffer or create a temporary one. in dw_spi_init_mem_buf()
503 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; in dw_spi_init_mem_buf()
504 if (op->data.dir == SPI_MEM_DATA_OUT) in dw_spi_init_mem_buf()
505 len += op->data.nbytes; in dw_spi_init_mem_buf()
508 out = dws->buf; in dw_spi_init_mem_buf()
512 return -ENOMEM; in dw_spi_init_mem_buf()
520 for (i = 0; i < op->cmd.nbytes; ++i) in dw_spi_init_mem_buf()
521 out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1); in dw_spi_init_mem_buf()
522 for (j = 0; j < op->addr.nbytes; ++i, ++j) in dw_spi_init_mem_buf()
523 out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1); in dw_spi_init_mem_buf()
524 for (j = 0; j < op->dummy.nbytes; ++i, ++j) in dw_spi_init_mem_buf()
527 if (op->data.dir == SPI_MEM_DATA_OUT) in dw_spi_init_mem_buf()
528 memcpy(&out[i], op->data.buf.out, op->data.nbytes); in dw_spi_init_mem_buf()
530 dws->n_bytes = 1; in dw_spi_init_mem_buf()
531 dws->tx = out; in dw_spi_init_mem_buf()
532 dws->tx_len = len; in dw_spi_init_mem_buf()
533 if (op->data.dir == SPI_MEM_DATA_IN) { in dw_spi_init_mem_buf()
534 dws->rx = op->data.buf.in; in dw_spi_init_mem_buf()
535 dws->rx_len = op->data.nbytes; in dw_spi_init_mem_buf()
537 dws->rx = NULL; in dw_spi_init_mem_buf()
538 dws->rx_len = 0; in dw_spi_init_mem_buf()
546 if (dws->tx != dws->buf) in dw_spi_free_mem_buf()
547 kfree(dws->tx); in dw_spi_free_mem_buf()
557 * At initial stage we just pre-fill the Tx FIFO in with no rush, in dw_spi_write_then_read()
561 len = min(dws->fifo_len, dws->tx_len); in dw_spi_write_then_read()
562 buf = dws->tx; in dw_spi_write_then_read()
563 while (len--) in dw_spi_write_then_read()
569 * otherwise the CS de-assertion will happen whereupon the memory in dw_spi_write_then_read()
570 * operation will be pre-terminated. in dw_spi_write_then_read()
572 len = dws->tx_len - ((void *)buf - dws->tx); in dw_spi_write_then_read()
575 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR); in dw_spi_write_then_read()
577 dev_err(&dws->host->dev, "CS de-assertion on Tx\n"); in dw_spi_write_then_read()
578 return -EIO; in dw_spi_write_then_read()
580 room = min(dws->fifo_len - entries, len); in dw_spi_write_then_read()
581 for (; room; --room, --len) in dw_spi_write_then_read()
586 * Data fetching will start automatically if the EEPROM-read mode is in dw_spi_write_then_read()
590 len = dws->rx_len; in dw_spi_write_then_read()
591 buf = dws->rx; in dw_spi_write_then_read()
593 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR); in dw_spi_write_then_read()
595 sts = readl_relaxed(dws->regs + DW_SPI_RISR); in dw_spi_write_then_read()
597 dev_err(&dws->host->dev, "FIFO overflow on Rx\n"); in dw_spi_write_then_read()
598 return -EIO; in dw_spi_write_then_read()
603 for (; entries; --entries, --len) in dw_spi_write_then_read()
623 ns = NSEC_PER_SEC / dws->current_freq * nents; in dw_spi_wait_mem_op_done()
624 ns *= dws->n_bytes * BITS_PER_BYTE; in dw_spi_wait_mem_op_done()
634 while (dw_spi_ctlr_busy(dws) && retry--) in dw_spi_wait_mem_op_done()
638 dev_err(&dws->host->dev, "Mem op hanged up\n"); in dw_spi_wait_mem_op_done()
639 return -EIO; in dw_spi_wait_mem_op_done()
654 * devices, which are selected by the native chip-select lane. It's
655 * specifically developed to workaround the problem with automatic chip-select
657 * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
662 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); in dw_spi_exec_mem_op()
676 * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN in dw_spi_exec_mem_op()
677 * operation. Transmit-only mode is suitable for the rest of them. in dw_spi_exec_mem_op()
680 cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); in dw_spi_exec_mem_op()
681 if (op->data.dir == SPI_MEM_DATA_IN) { in dw_spi_exec_mem_op()
683 cfg.ndf = op->data.nbytes; in dw_spi_exec_mem_op()
690 dw_spi_update_config(dws, mem->spi, &cfg); in dw_spi_exec_mem_op()
698 * (without any vendor-specific modifications) it doesn't provide a in dw_spi_exec_mem_op()
699 * direct way to set and clear the native chip-select signal. Instead in dw_spi_exec_mem_op()
701 * transmission is going on, and automatically de-asserts it back to in dw_spi_exec_mem_op()
703 * out. Due to that a multi-tasking or heavy IRQs activity might be in dw_spi_exec_mem_op()
705 * getting empty and sudden CS de-assertion, which in the middle of the in dw_spi_exec_mem_op()
707 * EEPROM-read or Read-only DW SPI transfer modes imply the incoming in dw_spi_exec_mem_op()
711 * sure the executed memory operations are CS-atomic and to prevent the in dw_spi_exec_mem_op()
716 * the problems described above. The CS de-assertion and Rx FIFO in dw_spi_exec_mem_op()
718 * CPU not working fast enough, so the write-then-read algo implemented in dw_spi_exec_mem_op()
722 * dws->max_mem_freq parameter. in dw_spi_exec_mem_op()
727 ret = dw_spi_write_then_read(dws, mem->spi); in dw_spi_exec_mem_op()
734 * status only if there hasn't been any run-time error detected. In the in dw_spi_exec_mem_op()
745 dw_spi_stop_mem_op(dws, mem->spi); in dw_spi_exec_mem_op()
758 * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
759 * be safer to use the normal SPI-messages-based transfers implementation.
763 if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && in dw_spi_init_mem_ops()
764 !dws->set_cs) { in dw_spi_init_mem_ops()
765 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size; in dw_spi_init_mem_ops()
766 dws->mem_ops.supports_op = dw_spi_supports_mem_op; in dw_spi_init_mem_ops()
767 dws->mem_ops.exec_op = dw_spi_exec_mem_op; in dw_spi_init_mem_ops()
768 if (!dws->max_mem_freq) in dw_spi_init_mem_ops()
769 dws->max_mem_freq = dws->max_freq; in dw_spi_init_mem_ops()
776 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup()
782 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup()
787 return -ENOMEM; in dw_spi_setup()
789 /* Get specific / default rx-sample-delay */ in dw_spi_setup()
790 if (device_property_read_u32(&spi->dev, in dw_spi_setup()
791 "rx-sample-delay-ns", in dw_spi_setup()
794 rx_sample_dly_ns = dws->def_rx_sample_dly_ns; in dw_spi_setup()
795 chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns, in dw_spi_setup()
797 dws->max_freq); in dw_spi_setup()
805 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()
825 * by the platform. CoreKit version ID is encoded as a 3-chars ASCII in dw_spi_hw_init()
826 * code enclosed with '*' (typical for the most of Synopsys IP-cores). in dw_spi_hw_init()
828 if (!dws->ver) { in dw_spi_hw_init()
829 dws->ver = dw_readl(dws, DW_SPI_VERSION); in dw_spi_hw_init()
833 DW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2), in dw_spi_hw_init()
834 DW_SPI_GET_BYTE(dws->ver, 1)); in dw_spi_hw_init()
838 * Try to detect the number of native chip-selects if the platform in dw_spi_hw_init()
841 if (!dws->num_cs) { in dw_spi_hw_init()
848 dws->num_cs = hweight16(ser); in dw_spi_hw_init()
855 if (!dws->fifo_len) { in dw_spi_hw_init()
865 dws->fifo_len = (fifo == 1) ? 0 : fifo; in dw_spi_hw_init()
866 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); in dw_spi_hw_init()
884 dws->caps |= DW_SPI_CAP_DFS32; in dw_spi_hw_init()
885 dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK); in dw_spi_hw_init()
886 dev_dbg(dev, "Detected 32-bits max data frame size\n"); in dw_spi_hw_init()
889 dws->caps |= DW_SPI_CAP_DFS32; in dw_spi_hw_init()
893 if (dws->caps & DW_SPI_CAP_CS_OVERRIDE) in dw_spi_hw_init()
903 return -EINVAL; in dw_spi_add_host()
907 return -ENOMEM; in dw_spi_add_host()
909 device_set_node(&host->dev, dev_fwnode(dev)); in dw_spi_add_host()
911 dws->host = host; in dw_spi_add_host()
912 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); in dw_spi_add_host()
919 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), in dw_spi_add_host()
921 if (ret < 0 && ret != -ENOTCONN) { in dw_spi_add_host()
928 host->use_gpio_descriptors = true; in dw_spi_add_host()
929 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; in dw_spi_add_host()
930 if (dws->caps & DW_SPI_CAP_DFS32) in dw_spi_add_host()
931 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in dw_spi_add_host()
933 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in dw_spi_add_host()
934 host->bus_num = dws->bus_num; in dw_spi_add_host()
935 host->num_chipselect = dws->num_cs; in dw_spi_add_host()
936 host->setup = dw_spi_setup; in dw_spi_add_host()
937 host->cleanup = dw_spi_cleanup; in dw_spi_add_host()
938 if (dws->set_cs) in dw_spi_add_host()
939 host->set_cs = dws->set_cs; in dw_spi_add_host()
941 host->set_cs = dw_spi_set_cs; in dw_spi_add_host()
942 host->transfer_one = dw_spi_transfer_one; in dw_spi_add_host()
943 host->handle_err = dw_spi_handle_err; in dw_spi_add_host()
944 if (dws->mem_ops.exec_op) in dw_spi_add_host()
945 host->mem_ops = &dws->mem_ops; in dw_spi_add_host()
946 host->max_speed_hz = dws->max_freq; in dw_spi_add_host()
947 host->flags = SPI_CONTROLLER_GPIO_SS; in dw_spi_add_host()
948 host->auto_runtime_pm = true; in dw_spi_add_host()
951 device_property_read_u32(dev, "rx-sample-delay-ns", in dw_spi_add_host()
952 &dws->def_rx_sample_dly_ns); in dw_spi_add_host()
954 if (dws->dma_ops && dws->dma_ops->dma_init) { in dw_spi_add_host()
955 ret = dws->dma_ops->dma_init(dev, dws); in dw_spi_add_host()
956 if (ret == -EPROBE_DEFER) { in dw_spi_add_host()
961 host->can_dma = dws->dma_ops->can_dma; in dw_spi_add_host()
962 host->flags |= SPI_CONTROLLER_MUST_TX; in dw_spi_add_host()
976 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_add_host()
977 dws->dma_ops->dma_exit(dws); in dw_spi_add_host()
980 free_irq(dws->irq, host); in dw_spi_add_host()
991 spi_unregister_controller(dws->host); in dw_spi_remove_host()
993 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_remove_host()
994 dws->dma_ops->dma_exit(dws); in dw_spi_remove_host()
998 free_irq(dws->irq, dws->host); in dw_spi_remove_host()
1006 ret = spi_controller_suspend(dws->host); in dw_spi_suspend_host()
1017 dw_spi_hw_init(&dws->host->dev, dws); in dw_spi_resume_host()
1018 return spi_controller_resume(dws->host); in dw_spi_resume_host()