Lines Matching +full:de +full:- +full:assertion
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
22 - ranges: Must be set up to reflect the memory layout with three integer values
23 for each chip-select line in use (only one entry is supported, see below
25 <cs-number> <offset> <physical address of mapping> <size>
27 Note that the GMI controller does not have any internal chip-select address
28 decoding, because of that chip-selects either need to be managed via software
29 or by employing external chip-select decoding logic.
31 If external chip-select logic is used to support multiple devices it is assumed
34 child device is supported which represents the active chip-select line, see
37 The chip-select number is decoded from the child nodes second address cell of
38 'ranges' property, if 'ranges' property is not present or empty chip-select will
43 - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
44 - nvidia,snor-mux-mode: Enable address/data MUX mode.
45 - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
47 - nvidia,snor-rdy-active-high: RDY signal is active high
48 - nvidia,snor-adv-active-high: ADV signal is active high
49 - nvidia,snor-oe-active-high: WE/OE signal is active high
50 - nvidia,snor-cs-active-high: CS signal is active high
56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
57 bus. Valid values are 0-15, default is 1
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
59 de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
60 (in case of MASTER Request). Valid values are 0-15, default is 1
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
62 Valid values are 0-15, default is 1.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
64 Valid values are 0-15, default is 4
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
66 Valid values are 0-15, default is 1
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
68 Valid values are 0-255, default is 1
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
70 Valid values are 0-255, default is 3
73 controllers with a simple-bus node since they are all connected to the same
74 chip-select (CS4), in this example external address decoding is provided:
77 compatible = "nvidia,tegra20-gmi";
79 #address-cells = <2>;
80 #size-cells = <1>;
82 clock-names = "gmi";
84 reset-names = "gmi";
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
93 nvidia,snor-mux-mode;
94 nvidia,snor-adv-active-high;
112 compatible = "nvidia,tegra20-gmi";
114 #address-cells = <2>;
115 #size-cells = <1>;
117 clock-names = "gmi";
119 reset-names = "gmi";
124 nvidia,snor-mux-mode;
125 nvidia,snor-adv-active-high;