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/linux/Documentation/devicetree/bindings/perf/
H A Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
[all …]
H A Damlogic,g12-ddr-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic G12 DDR performance monitor
10 - Jiucheng Xu <jiucheng.xu@amlogic.com>
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
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H A Dmarvell-cn10k-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K DDR performance monitor
10 - Bharat Bhushan <bbhushan2@marvell.com>
15 - enum:
16 - marvell,cn10k-ddr-pmu
22 - compatible
23 - reg
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/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
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H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
42 * 32bit counters monitor counter-specific events in addition to counting reference events
59 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
74 * respecitively to counter 2-5.
79 const char *identifier; /* system PMU identifier for userspace */
84 struct pmu pmu; member
117 static inline bool axi_filter_v1(struct ddr_pmu *pmu) in axi_filter_v1() argument
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
122 static inline bool axi_filter_v2(struct ddr_pmu *pmu) in axi_filter_v2() argument
124 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
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H A Dalibaba_uncore_drw_pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Alibaba DDR Sub-System Driveway PMU driver
55 /* PMU EVENT SEL 0-3 are paired in 32-bit registers on a 4-byte stride */
57 /* counter 0-3 use sel0, counter 4-7 use sel1...*/
65 /* PMU COMMON COUNTER 0-15, are paired in 32-bit registers on a 4-byte stride */
105 struct pmu pmu; member
108 #define to_ali_drw_pmu(p) (container_of(p, struct ali_drw_pmu, pmu))
111 #define GET_DRW_EVENTID(event) FIELD_GET(DRW_CONFIG_EVENTID, (event)->attr.config)
120 return sprintf(buf, "%s\n", (char *)eattr->var); in ali_drw_pmu_format_show()
124 * PMU event attributes
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/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
18 The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
19 For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
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H A Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 hisi-pcie-pmu
12 hns3-pmu
13 imx-ddr
17 mrvl-odyssey-ddr-pmu
18 mrvl-odyssey-tad-pmu
19 arm-ccn
20 arm-cmn
21 arm-ni
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H A Dhisi-pmu.rst2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
15 HiSilicon SoC uncore PMU driver
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
39 ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is
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H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
40 - 0: corresponding bit is masked.
[all …]
H A Dmeson-ddr-pmu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
24 Below are DDR access request event filter keywords:
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
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H A Dfujitsu_uncore_pmu.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Fujitsu Uncore Performance Monitoring Unit (PMU)
9 Each MAC PMU on these chips is exposed as a uncore perf PMU with device name
11 And each PCI PMU on these chips is exposed as a uncore perf PMU with device name
19 - formats, used by perf user space and other tools to configure events
20 - events, used by perf user space and other tools to create events
23 perf stat -a -e mac_iod0_mac0_ch0/event=0x21/ ls
24 perf stat -a -e pci_iod0_pci0/event=0x24/ ls
26 - cpumask, used by perf user space and other tools to know on which CPUs
31 - cycles
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
H A Dimx8-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
26 clock-names:
28 - const: dmc_clk
[all …]
/linux/drivers/perf/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
10 tristate "HiSilicon PCIE PERF PMU"
13 Provide support for HiSilicon PCIe performance monitoring unit (PMU)
15 Adds the PCIe PMU into perf events system for monitoring latency,
19 tristate "HNS3 PERF PMU"
23 Provide support for HNS3 performance monitoring unit (PMU) RCiEP
25 Adds the HNS3 PMU into perf events system for monitoring latency,
/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
/linux/drivers/devfreq/
H A Drk3399_dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
12 #include <linux/devfreq-event.h>
75 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
99 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target()
100 * Firmware power-domain idling. in rk3399_dmcfreq_target()
104 dev_err(dev, "Failed to block PMU: %d\n", err); in rk3399_dmcfreq_target()
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H A Dsun8i-a33-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (C) 2020-2021 Samuel Holland <samuel@sholland.org>
25 #define MBUS_TMR_PERIOD(x) ((x) - 1)
28 #define MBUS_PMU_CFG_PERIOD(x) (((x) - 1) << 16)
107 /* Returns the peak transfer (in KiB) during any single PMU period. */ in sun8i_a33_mbus_get_peak_bw()
108 return readl_relaxed(priv->reg_mbus + MBUS_TOTAL_BWCR); in sun8i_a33_mbus_get_peak_bw()
115 /* All PMU counters are cleared on a disable->enable transition. */ in sun8i_a33_mbus_restart_pmu_counters()
117 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
119 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
127 * Nominal bandwidth (KiB per PMU period): in sun8i_a33_mbus_update_nominal_bw()
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/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c2 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <pmu-events/pmu-events.h>
7 #include "util/pmu.h"
23 /* offset=9 */ "cpu-clock\000software\000Per-CPU high-resolution timer based event\000config=0\000\…
24 /* offset=87 */ "task-clock\000software\000Per-task high-resolution timer based event\000config=1\0…
25 /* offset=167 */ "faults\000software\000Number of page faults [This event is an alias of page-fault…
26 /* offset=262 */ "page-faults\000software\000Number of page faults [This event is an alias of fault…
27 /* offset=357 */ "context-switches\000software\000Number of context switches [This event is an alia…
28 /* offset=458 */ "cs\000software\000Number of context switches [This event is an alias of context-s…
29 /* offset=559 */ "cpu-migrations\000software\000Number of times a process has migrated to a new CPU…
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
[all …]
/linux/arch/arm64/boot/dts/blaize/
H A Dblaize-blzp1600.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
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